Is it possible to create an own (individual configured) Xilinx JTAG Hardware Co-simulation Block in the System Generator without generating the block inside System Generator?
The idea is, the generate the bit-File outside the System Generator software and use System Generator / MatLab only for generating and analysing data.
I saw that it is possible to change the bitstream name in the Co-Sim block but how can I change ports etc.?
A default/empty "JTAG Co-sim" doesn't seem to be exist in the library.
Thanks in advance!