cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
1,636 Views
Registered: ‎07-01-2018

Tcl script errors when generating example for Video DisplayPort 1.4 RX Subsystem IP

Jump to solution

I'm trying to create the example design for the Video DisplayPort 1.4 RX Subsystem IP. I follow the steps as described in chapter 5 of document PG300.

But I get Tcl script errors when the design is created.

(I also tried version Vivado 2018.1 but that one when gives even more errors)

 

Anybody an idea what is wrong?

 

This is the output of the Tcl Console:

 

====================================================================================================
Sourcing tcl script 'C:/Xilinx/Vivado/2018.2/scripts/Vivado_init.tcl'
Set Board Part RepoPath: M:/System/Xilinx/board_files
start_gui
source m:/vivado_project/project_3/.Xil/v_dp_rxss1_0/tmp_v_dp_rxss1_0.srcs/sources_1/ip/v_dp_rxss1_0/v_dp_rxss1_0_ex.tcl -notrace
INFO: [open_example_project] Creating new example project...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2018.2/data/ip'.
create_project: Time (s): cpu = 00:00:15 ; elapsed = 00:00:06 . Memory (MB): peak = 883.180 ; gain = 135.684
INFO: [open_example_project] Adding example synthesis miscellaneous files ...
INFO: [open_example_project] Adding example XDC files ...
INFO: [open_example_project] Sourcing example extension scripts ...
zynquplus
WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_es1:part0:1.0 available at M:/System/Xilinx/board_files/TE0803_ES1/1.0/board.xml as part xczu3eg-sfvc784-1-i-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part trenz.biz:te0803_es1_tebf0808:part0:2.0 available at M:/System/Xilinx/board_files/TE0803_ES1/2.0/board.xml as part xczu3eg-sfvc784-1-i-es1 specified in board_part file is either invalid or not available
INFO: [BD_TCL-3] Currently there is no design <v_dp_rxss1_0_design_synth> in project, so creating one...
Wrote  : <m:/vivado_project/examples/v_dp_rxss1_0_ex/v_dp_rxss1_0_ex.srcs/sources_1/bd/v_dp_rxss1_0_design_synth/v_dp_rxss1_0_design_synth.bd>
create_bd_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 978.652 ; gain = 87.102
INFO: [BD_TCL-4] Making design <v_dp_rxss1_0_design_synth> as current_bd_design.
INFO: [BD_TCL-5] Currently the variable <design_name> is equal to "v_dp_rxss1_0_design_synth".
INFO: [BD_TCL-6] Checking if the following IPs exist in the project's IP catalog: 
xilinx.com:ip:axi_iic:2.0 xilinx.com:ip:axi_timer:2.0 xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:system_ila:1.1 xilinx.com:ip:util_vector_logic:2.0 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:zynq_ultra_ps_e:3.2 xilinx.com:ip:util_ds_buf:2.1 xilinx.com:ip:util_reduced_logic:2.0 xilinx.com:ip:v_dp_rxss1:1.0 xilinx.com:ip:vid_edid:1.0 xilinx.com:ip:vid_phy_controller:2.2 xilinx.com:ip:video_frame_crc:1.0  .
create_bd_cell: Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 2075.176 ; gain = 1072.891
BEGIN1: update_boundary
INFO: [Device 21-403] Loading part xczu9eg-ffvb1156-2-e
create_bd_cell: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 2268.016 ; gain = 173.758
WARNING: [BD 41-1284] Cannot set parameter SUGGESTED_PRIORITY on port /dprxss_dp_irq
BEGIN1: update_boundary
create_bd_cell: Time (s): cpu = 00:00:25 ; elapsed = 00:00:31 . Memory (MB): peak = 2284.770 ; gain = 207.441
create_bd_cell: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2289.168 ; gain = 4.293
WARNING: [IP_Flow 19-2162] IP 'bd_aec7_dp_0_rs_decoder_v9_0_14_viv' is locked:
* IP 'bd_aec7_dp_0_rs_decoder_v9_0_14_viv' requires one or more mandatory licenses but no valid licenses were found. However license checkpoints may prevent use of this IP in some tool flows.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
ERROR: [Common 17-107] Cannot change read-only property 'CONFIG.aclken'.
Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.2/data/ip/xilinx/displayport_v8_0/ttcl/rs_decoder_elaborate.xit': ERROR: [Common 17-107] Cannot change read-only property 'CONFIG.aclken'.
Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'dp_rx_hier_0/v_dp_rxss1_0/U0/dp'. Failed to generate 'Elaborate Sub-Cores' outputs:
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2018.2/data/ip/xilinx/v_dp_rxss1_v1_0/elaborate/bd.xit': ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'dp_rx_hier_0/v_dp_rxss1_0'. Failed to generate 'Elaborate BD' outputs: Failed to elaborate IP.
BEGIN1: update_boundary
create_bd_cell: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2307.098 ; gain = 0.000
WARNING: [BD 41-1284] Cannot set parameter SUGGESTED_PRIORITY on port /dprxss_dp_irq
INFO: [IP_Flow 19-3438] Customization errors found on 'dp_rx_hier_0/v_dp_rxss1_0'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [open_example_project] Open Example Project failed: Error encountered while sourcing custom IP example design script.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::add_properties -dict {CONFIG.AUDIO_ENABLE 1 CONFIG.AUX_IO_LOC 1 CONFIG.BITS_PER_COLOR 10 CONFIG.PHY_DATA_WIDTH 2} /dp_rx_hier_0/v_dp_rxss1_0"
    invoked from within
"set_property -dict [ list  CONFIG.AUDIO_ENABLE {1}  CONFIG.AUX_IO_LOC {1}  CONFIG.BITS_PER_COLOR {10}  CONFIG.PHY_DATA_WIDTH {2}  ] $v_dp_rxss1_0"
    (procedure "create_hier_cell_dp_rx_hier_0" line 89)
    invoked from within
"create_hier_cell_dp_rx_hier_0 [current_bd_instance .] dp_rx_hier_0"
    (procedure "create_root_design" line 67)
    invoked from within
"create_root_design """
    (file "m:/vivado_project/examples/v_dp_rxss1_0_ex/imports/exdes_zcu102_rx.tcl" line 2094)
    invoked from within
"source [get_property directory [current_project]]/imports/exdes_zcu102_rx.tcl"
    invoked from within
"if {[regexp $ZYNQUPLUS $device_family] == 1 || [regexp $KUPLUS $device_family] == 1} {
    set boardparts [get_board_parts xilinx.com:zcu102:* -latest_fi..."
    (file "m:/vivado_project/project_3/.Xil/v_dp_rxss1_0/tmp_v_dp_rxss1_0.srcs/sources_1/ip/v_dp_rxss1_0/v_dp_rxss1_0_exdes_bd_synth.tcl" line 20)
    invoked from within
"source [file join $srcIpDir v_dp_rxss1_0_exdes_bd_synth.tcl]"
ERROR: see log file for details.
    while executing
"error "ERROR: see log file for details.""
    invoked from within
"if {[catch {source [file join $srcIpDir v_dp_rxss1_0_exdes_bd_synth.tcl]} errMsg]} {
  puts "ERROR: \[open_example_project\] Open Example Project fail..."
    (file "m:/vivado_project/project_3/.Xil/v_dp_rxss1_0/tmp_v_dp_rxss1_0.srcs/sources_1/ip/v_dp_rxss1_0/v_dp_rxss1_0_ex.tcl" line 59)
update_compile_order -fileset sources_1
====================================================================================================

Best Regards

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
1,557 Views
Registered: ‎11-09-2015

Hi @cor,

 

@watari is right. It is a licensing issue. You can see from your log:

 

* IP 'bd_aec7_dp_0_rs_decoder_v9_0_14_viv' requires one or more mandatory licenses but no valid licenses were found. 
However license checkpoints may prevent use of this IP in some tool flows.

 

 

You need to have a valid license to generate the DP1.4 example design. You can generate an HW evaluation license from the IP product page. Just click on Evaluate.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

5 Replies
Highlighted
Teacher
Teacher
1,614 Views
Registered: ‎06-16-2013

Hi @cor

 

Do you have a valid licence for Display Port IP ?

It seems licence issue.

 

Best regards,

Highlighted
Visitor
Visitor
1,605 Views
Registered: ‎07-01-2018

I assumed we can use the IP to be able to develop with it.And that it only workes for an hour each time or so.

Can I get some temporary license?

Cor

0 Kudos
Highlighted
Visitor
Visitor
1,575 Views
Registered: ‎07-01-2018

Hi,

How do you see that it would be a license problem? I do not see errors pointing that out.

And do we really need a license to be able to generate and investigate the example design?

 

0 Kudos
Highlighted
Moderator
Moderator
1,558 Views
Registered: ‎11-09-2015

Hi @cor,

 

@watari is right. It is a licensing issue. You can see from your log:

 

* IP 'bd_aec7_dp_0_rs_decoder_v9_0_14_viv' requires one or more mandatory licenses but no valid licenses were found. 
However license checkpoints may prevent use of this IP in some tool flows.

 

 

You need to have a valid license to generate the DP1.4 example design. You can generate an HW evaluation license from the IP product page. Just click on Evaluate.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Highlighted
Visitor
Visitor
1,543 Views
Registered: ‎07-01-2018

That worked! Thx

0 Kudos