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Contributor
Contributor
1,189 Views
Registered: ‎11-10-2017

Timing Error in MIPI CSI2 Rx Subsystem IP

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Hi, I'm using this design.

https://github.com/Digilent/Zybo-Z7-20-base-linux

This design uses MIPI CSI2 Rx Subsystem IP to get image from PCam 5C via MIPI standard.

By using this design, we can get PCam camera image on Linux on ZYBO Z7-20.

 

I have cloned this repository, and run implementation.

I got the following timing error. It seems that the timing error exists inside MIPI CSI2 Rx Subsystem IP.

Screenshot from 2018-11-29 16-52-49.pngScreenshot from 2018-11-29 16-52-07.png

Although timing error exists, I confirmed that ZYBO got PCam 5C  camera image correctly.

But I want to know the reason why timing error exists, and modify the problem.

 

Do you have any solution? Thanks in advance.

- Vivado Version : 2017.4 on Ubuntu 16.04

- MIPI CSI2 Rx Subsystem Version: 3.0

NOTE:

1) To use MIPI CSI2 Rx Subsystem, you need Xilinx Logicore Licence.

2) When I run create_project.tcl, I got the following error and tcl running stopped.

WARNING: [Vivado 12-818] No files matched '*/home/takagilab/fpt_vivado/Zybo-Z7-20-base-linux/src/bd/bd_0ac3 system/bd_0ac3 system.bd'
ERROR: [Common 17-55] 'get_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

So, I created HDL wrapper files by myself. (I think this is not related to this problem)

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Xilinx Employee
Xilinx Employee
1,138 Views
Registered: ‎03-30-2016

Hello @nittax

>Although timing error exists, I confirmed that ZYBO got PCam 5C  camera image correctly.

Congratulation. I am happy to hear that.

1. I've seen similar timing violation reports on customer design using 7-series with speedgrade:-1.
   Especially with a larger design.
   
2. Do you have any access 7-series device with speedgrade:-2 ?
   If yes, could you please try to migrate your design ?

3. These timing violations are doing no harm to your design.
   Failing paths are  HS_settle_reg & init_reg registers connectivity inside the core.
   Actually these are static paths, so you can safely ignore it.
   
4. Could you please try MIPI IP from Vivado 2018.3 ??

   We had some modification around HS_settle_regs path, so timing improvement is also expected.
   Vivado 2018.3 will be release soon. Very soon.
   
Thanks & regards
Leo

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Teacher
Teacher
1,173 Views
Registered: ‎06-16-2013

Hi @nittax

 

> But I want to know the reason why timing error exists, and modify the problem.

 

I suggest to read the following URL.

https://en.wikipedia.org/wiki/Process_corners

 

In my experience, it is hardly to archive 200MHz on ZYBO, if congestion is high.

If you resolved this issue, I suggest changing device or considering an archtechture and/or bus width.

 

Best regards,

 

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Xilinx Employee
Xilinx Employee
1,139 Views
Registered: ‎03-30-2016

Hello @nittax

>Although timing error exists, I confirmed that ZYBO got PCam 5C  camera image correctly.

Congratulation. I am happy to hear that.

1. I've seen similar timing violation reports on customer design using 7-series with speedgrade:-1.
   Especially with a larger design.
   
2. Do you have any access 7-series device with speedgrade:-2 ?
   If yes, could you please try to migrate your design ?

3. These timing violations are doing no harm to your design.
   Failing paths are  HS_settle_reg & init_reg registers connectivity inside the core.
   Actually these are static paths, so you can safely ignore it.
   
4. Could you please try MIPI IP from Vivado 2018.3 ??

   We had some modification around HS_settle_regs path, so timing improvement is also expected.
   Vivado 2018.3 will be release soon. Very soon.
   
Thanks & regards
Leo

View solution in original post

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Moderator
Moderator
1,039 Views
Registered: ‎11-09-2015

HI @nittax,

Do you have any updates on this? 2018.3 is now released, is it possible for you to try and check if you see any improvements?

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
922 Views
Registered: ‎11-10-2017

@karnanl @florentw I'm sorry for very late reply.

I have synthesized the project in Vivado 2018.3.

I have confirmed that timing error is NOT occurred!!

Thank you.

スクリーンショット 2019-01-15 09.16.01.png