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shahan.a
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Participant
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Registered: ‎06-25-2019

Transciever initialization not starting for HDMI TX design

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Hi all,

I am working on a design with the HDMI TX subsystem. The HDMI TX subsystem and Video Phy Controller are configured for 4 pixels per clock. I am using CPLL as PLL. When testing the design on a board, after mode setting the HDMI TX to display 3840x2160 @ 60 FPS output the transceiver initialization doesn't seem to start. The 'TXRESETDONE' signal coming from the three transceivers never went high. . GTTXRESETIN is always high, it doesn't go low. I have attached a screenshot of the signals I probed in the ILA.gt_tx_reset_2_txresetdone_out.jpg

 What could be the reason for transciever initialization not starting?

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shahan.a
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Participant
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Registered: ‎06-25-2019

Hi all,

I have figured out the cause of the problem. The issue was because the Clock synthesizer was not getting programmed to the correct clock frequency because the frequency specified for the clock synthesizer crystal oscillator was wrong in the device tree and also some modifications for the clock synthesizer driver were required. After these modifications, the Transceiver initialization proceeded.

 

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xud
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@shahan.a 

Do you see this issue with other resolution, like 1080p60? How do you generate the GT reference clock, and drive the tx_refclk_rdy?

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shahan.a
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Registered: ‎06-25-2019

Hi @xud,

I hadn't tested with other resolutions, I will test that. The GT reference clock is generated using an external clock synthesizer(SI5345B-D-GM). tx_refclk_rdy is active high. I drive the tx_refclk_rdy high by writing '1' to a register. And also to ensure the clock at txrefclk_p/n ports are stable, I assert the tx_refclk_rdy sometime after powering on the board.

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shahan.a
Participant
Participant
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Registered: ‎06-25-2019

Hi all,

I have figured out the cause of the problem. The issue was because the Clock synthesizer was not getting programmed to the correct clock frequency because the frequency specified for the clock synthesizer crystal oscillator was wrong in the device tree and also some modifications for the clock synthesizer driver were required. After these modifications, the Transceiver initialization proceeded.

 

View solution in original post

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