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guerric.mdd
Participant
Participant
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Registered: ‎12-18-2017

Use of multiple GT in a Quad for UHD-SDI on Kintex Ultrascale+ ?

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Hello,

 

It looks to me that using multiple GTs in a quad for UHD-SDI on Kintex Ultrascale+ is not working.

 

I started from example design for KCU116, generated from the UHD-SDI RX SS, using Vivado 2018.1. I'm therefore using GTYs.

I then made the few modifications necessary for me (namely using another quad because I'm using SDI SFPs instead of an FMC module).

I could compile the project and check that SDI video was working as expected (I didn't check audio part).

 

I then added more than 1 GT in the quad by customizing the UHD-SDI GT IP. I then realized that while GT1 is connected, the 3 other GTs are unconnected. The compilation fails because constraints about 3 of the GT connections are not correct (since they are unconnected). That is not obvious but the following post-implementation schematic screenshot shows that 3 GT TX are not connected to GT (because of use of OBUF and because Vivado picks "random" FPGA pins for them). For RX, I know from reports and other attempts that 3 GT are unconnected:

 1GT_outof4_crop.png

 

And here is how I connected the UHD-SDI GT IP. I simply connected ports / logic from example design to 4th GT and chained IN/OUT for the 3 others:

GTconfig.png

 

Any idea on how to make use of more than 1 GT in the quad for UHD-SDI GT IP?

Thanks in advance.

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florentw
Moderator
Moderator
2,271 Views
Registered: ‎11-09-2015

The issue is documented in AR#70994.

 

The patch can be found in AR#70974.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
Moderator
Moderator
1,899 Views
Registered: ‎11-09-2015

Hi @guerric.mdd,

 

To clarify:

When you say you added on more GT, go you mean you increased the number of links in the UHD-SDI GT core?

 

If this is the case, there is a known issue. Development is working on it.

 

Could you try by using 2 different UHD-SDI GT with only one with the GT common (using Figure C-4 from pg2902 as reference)?

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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guerric.mdd
Participant
Participant
1,891 Views
Registered: ‎12-18-2017

Hello Florent,

 

I moved from 1 to 4 links in the UHD-SDI GT core indeed.

Do you know how long will it take for development to solve this? Is it more about 2 weeks or 3 months?

I will try what you suggest (PG290, figure C-4).

 

Thanks!

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florentw
Moderator
Moderator
1,883 Views
Registered: ‎11-09-2015

Hi @guerric.mdd,

 

I hope the issue to be fixed in few weeks. But I cannot garanty anything.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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florentw
Moderator
Moderator
1,863 Views
Registered: ‎11-09-2015

Hi @guerric.mdd,

 

I sent you the patch which should become public in the next few days.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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florentw
Moderator
Moderator
2,272 Views
Registered: ‎11-09-2015

The issue is documented in AR#70994.

 

The patch can be found in AR#70974.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post