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Voyager
Voyager
1,050 Views
Registered: ‎03-17-2011

VCU-TRD : clock constraints

hi,

 

I have a created a design based on the VCU TRD 2018.2. I had to extend the number of SDI Rx p to 4 links instead of one in the reference design.

Now I'm facing problems with declaring the clocks in the xdc file.

 

Therefore, I try to understand the contraints in teh sdirxtx_timing.xdc file but no luck so far.

the file starts with such commands:

 

set max_delay_clkout0 [expr ([get_property PERIOD [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0}]]]-0.1)]
set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hier -filter {name=~*GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0}]] $max_delay_clkout0
set_max_delay -datapath_only -from [get_clocks -of_objects [get_pins -hier -filter {name=~*GTHE4_CHANNEL_PRIM_INST/TXOUTCLK}]] -to [get_clocks -include_generated_clocks -of_objects [get_pins -hier -filter {name=~*/clk_wiz_0/inst/mmcme4_adv_inst/CLKOUT0}]] $max_delay_clkout0

 

get_clocks -of_objects [get_pins -hier -filter {name=~*GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}] ?????

I don't understand how this is possible with no create clock before on the transceivers...

 

altough this command works, it fails when I run it to the other transceivers of my design (located within the same quad). I must add that:

* I took care of the hierarchy (hd1, hd2, ...) in my search paths,

* the command get_pins -hier -filter {name=~*hd2*GTHE4_CHANNEL_PRIM_INST/RXOUTCLK} is not failing for each instance. and gives a correct path. but get_clocks -of_objects [get_pins -hier -filter {name=~*hd2*GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}] is failing.

 

Thanks for any help on this.

 

regards,

 

Sebastien

 

--Sebastien
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Xilinx Employee
Xilinx Employee
1,028 Views
Registered: ‎08-01-2007

@seboThe reason you don't see the create clock commands is that the solution is relying on the auto generated constraints that the IP produces.

 

Since you are mostly concerned with the UHD-SDI Hardware designs, I'm going to recommend looking at the UHD-SDI Subsystem pass-through example design that is documented in Chapter 5 of the SMPTE UHD-SDI Rx Subsystem Product Guide, PG290.  This will help you to understand the basic hardware design and constraints.  This design is only single channel, and only focuses on the UHD-SDI Subsystems, but it should be easier to understand than looking at the much more complex VCU TRD.

 

You can then also generate another design that does multi-channel version of the UHD-SDI Rx/Tx Subsystem and the UHD-SDI GT.  Then take a look at the constraints generated by the multi-channel design as well.

Then once you get a better understanding of the constraints in the standalone design you can go back to the VCU TRD UDH-SDI Rx/Tx design and see how they integrated the UHD-SDI Rx/Tx Subsystems in the VCU TRD design.

Chris
Versal ACAP: AI Engines | Embedded SW Support

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Voyager
Voyager
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Registered: ‎03-17-2011

@chrisar,

 

Thanks for your answer. I had a look at the document. Then, I went to see the OOC contraints for the GT instances of my design (design_1_uhdsdi_gt_0_0 for instance).

Of course, constraints are all the same and I can see the following :

create_clock -period 3.367 [get_pins -hierarchical -filter {NAME =~ *gen_channel_container[2].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}]

Therefore, in OOC implementation, I should have one clock created by instance. And, they should be promoted/visible at top level. It's not the case.

 

When I run the get_pin command at top level, vivado gives only one path and not 4 paths (I have 4 instances). Then I can modify the contraint to create clocks using the hierarchy and it works.

create_clock -period 3.367 [get_pins -hierarchical -filter {NAME =~ *hd2*gen_channel_container[2].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}] 
create_clock -period 3.367 [get_pins -hierarchical -filter {NAME =~ *hd3*gen_channel_container[2].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}] 
create_clock -period 3.367 [get_pins -hierarchical -filter {NAME =~ *hd4*gen_channel_container[2].*gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST/RXOUTCLK}]

It's like constraints in OOC for 3 out of 4 instances of my GT are ignored or fall back to the first instance only.

 

What am I doing/understanding wrong?

 

Regards,

 

Sébastien

--Sebastien
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @sebo,

 

Could you try to open your implemented design on do write_xdc const.xdc. This should create a xdc file of all the constraints. This way you can really see if how many clock you have in all the constraints.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Voyager
Voyager
982 Views
Registered: ‎03-17-2011

hi @florentw,

 

I did that and went through the file.

There is no trace of the local constraints from the file system_basic_uhdsdi_gt_0_0_ooc.xdc. (this is where the clocks are created). Although the clock (at least for the first instance) exists when I run the report_clocks command.

 

I can only find the constraints for the file system_basic_uhdsdi_gt_0_0.xdc (for each instance).

 

 

--Sebastien
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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @sebo,

Sorry about the delay on this. What is your status?

I am quite sure the UHD-SDI_GT IP is creating the clocks. However, one thing I noticed is that when this is configured as Shared logic outside the core, the clock is not propagated. This is maybe why you are askng the question?

I have reported this to development to get a fix.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
783 Views
Registered: ‎11-09-2015

Hi @sebo,

In fact after analysis, the clocks seem to be defined directly from the BUFGT. They are only propagated through the UHD-SDI IP.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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