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pfarrokhi
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Registered: ‎10-31-2019

VCU decode and encode ports describtion

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Hi. I tried to use VCU example in zcu104 bsp to run a gstreamer command with PS RAM and it work. It have to encode port and two decode port and a MCU port. I have two question.

1) What is MCU port and where to connect?

2) Why there is two from each of encode and decode ports and i cant disable one of them and why all of them have access to all memory ports?

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florentw
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Registered: ‎11-09-2015

HI @pfarrokhi 

1) The MCU is a microcontroller located inside the VCU.

For the connection of all the ports of the VCU, please refer to PG252 chapter 11 - Desig flow step. Everything is documented

You can also use the ZCU104/ZCU106 BSP or VCU TRD as reference. The MCU also needs to access the memory (for the buffers).

2) There are 2 ports to allow more bandwith. This will be required if you want to achive the maximum performance. If you need to encode/decode low resolution, just connect the 2 ENC or DEC interface together through a smartconnect. But note that for many case, you need to have direct access to the zynq port to avoid congestion


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

HI @pfarrokhi 

1) The MCU is a microcontroller located inside the VCU.

For the connection of all the ports of the VCU, please refer to PG252 chapter 11 - Desig flow step. Everything is documented

You can also use the ZCU104/ZCU106 BSP or VCU TRD as reference. The MCU also needs to access the memory (for the buffers).

2) There are 2 ports to allow more bandwith. This will be required if you want to achive the maximum performance. If you need to encode/decode low resolution, just connect the 2 ENC or DEC interface together through a smartconnect. But note that for many case, you need to have direct access to the zynq port to avoid congestion


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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pfarrokhi
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Registered: ‎10-31-2019

Hi. Thank you for reply and sorry for my delay. I read that pdf before you say. Your idea for connecting two ports together is nice. But i still have problem with MCU connection. In bsp design that i used it was connected to AXI Interconnect beside one of the others ports. So i can't realize where to connect it exactly. Just connect it to Zynq processor or connect to PL RAM too, in case of using PL RAM.

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florentw
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Registered: ‎11-09-2015

HI @pfarrokhi 

I believe the MCU needs to be connected to the PS DDR as it needs to access the data cache. And the data cache will most likely be on your PS DDR (even if you could change that from the linker script but I do not recommend it).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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pfarrokhi
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Registered: ‎10-31-2019

So do you say that there is no need to connect it to PL RAM?

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florentw
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Registered: ‎11-09-2015

HI @pfarrokhi 

No I do not think it needs to be connected to the DDR.

But you might want to cross chekc with the following design which is using the PL DDR with the VCU:

Zynq UltraScale+ MPSoC VCU TRD 2019.1 - HDMI Video Capture and Display with PL DDR


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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pfarrokhi
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Registered: ‎10-31-2019

Ok. Thanks a lot.

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