VDMA Horizontal use with multiframes

[gicgatv]

Hi to all,

I'm working on a video project with Zynq 7Z020 and ZedBoard. I'm processing a video in more slices due to low fpga memory as follow:

 

A frame arrive and Is sequential processed slice by slice in order ABCD..N. To use FPGA parallelism and improve processing speed, I'm in the condition to process more frames at the same time as follow:

Where I should process  in order: frame1 A, frame2 B, frame3 C,... frame N D end than go to the next slice (Eg. ABCD ABCD ABCD ...).

I have created a Frame buffer that is able to charge N frames in Ram where the FPGA can read and write data.

I'm running in a problem where if I try to process more frames, the processing output is a blank image, while if I process only one frame It works correctly (but do not improve processing speed and is sequential).

I'd like to ask, Is the Axi VDMA that generate the problem? I suppose that the problem could be generated by Start of Frame signal(SOF). This could happen because, if I process the first part of the video a SOF arrive, after VDMA expects to receive the second slice. If in that moment a video slice from the second image is processed (a B slice that is the beginning of next frame) another SOF arrive and VDMA sync could fails. 

Is there a special VDMA configuration? Could I use VDMA in manual mode without internal sync? How can I solve this issue?

Many thanks in advance

[aoifem]

Hi @gicgatv 

Could you provide a bit more information on this issue? Could you provide a flow diagram to help me understand your dataflow? 

[gicgatv]

Hi Aoife

Thanks for Answer!

I have created 2 Flow chart, The first one is when I process data in a sequencial way Frame after frame:

While the second One is when I try to process the more frames from the buffer I have in RAM, slice by slice:

I hope to Help you understanding the issue.

Many Thanks in advance

[aoifem · Accepted solution]

Hi @gicgatv 

I think your understanding is correct, that the error is likely to be caused by the Start of Frame signal(SOF). 

Do you really need to go to memory? If not, I would suggest two options: 

1. Signal Processing

You can skip the memory completely if you just perform signal processing of the frames individually in the FPGA. If you need a buffer you can consider using a FIFO. 

You can use this option if all the streams are coming from different lanes (in parellel).

2. Custom IP 

If the input is in serial, you can create your own custom IP to take in the ABCD frames, divide them and output them as you desire. 

Regards, 

[aoifem]

Hi @gicgatv 

Do you have any update on this? 

If not, can you mark an answer as 'Accepted Solution' so other users can quickly find the answer in the future? 

If your issue is not resolved, please provide some more information and I will be happy to help. 

Regards,