06-19-2016 11:54 AM
I´d like to change the S2MM stream data width on the vdma settings or get rid of the auto mode, I want 24bits instead 32bits, all my design is on video stream of 24bits but despite that is not changing automatically:
Is it possible to change manually?,for instance using a TCL command?
Thanks in advance.
06-20-2016 06:47 AM
This setting will change to the width of whatever is driving it automatically. When you validate design, do you get any errors about mismatched port sizes or anything like that? If not, then it is adapting fine and you don't need to worry about the grayed out GUI.
06-20-2016 12:32 PM
06-20-2016 02:56 PM
Oh okay. Yeah I've seen sometimes the grayed out value doesn't change, but it doesn't matter. It'll be correct if there are no errors.
Unfortunately, there is no way to manually set it.
11-02-2016 02:19 PM
I am having issues with the auto detect feature for S2MM AXI-S width. I have a 16 bit signal going into the VDMA, and it is auto selecting 32 bit width. When I validate the design, it does come up with critical warnings saying the ports are mismatched, and the tool doesn't change it to make it match. To take it further, I decided to build a bit file anyway, and I can see that the data is being written into memory as 32 bit values, with the upper two bytes being zero. This means to me that the design never updated the bit width through synthesis/implementation, and is zero padding the upper two bytes. As there is no way to manually change the data width, how do I correct this issue?
04-19-2018 02:42 PM
Is there really no solution to this?? What if we manually go edit the verilog files? I have a design I am working on where I cannot get the width to change, no matter what I try. I tried disconnecting the individual lines which I had broken out and instead connected it to an AXI-stream bus that has a width of 119:0 but the tdata width on the VDMA will not change from 31:0. Any suggestions?
11-13-2018 11:16 PM
Just chiming in to say I'm seeing the same exact error, and it's preventing my build from working correctly. The bus width is not autodetected correctly, and I get a critical warning about the bus width mismatch. Surely there has to be a way to work around this problem.
11-16-2018 01:09 AM