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Contributor
Contributor
7,047 Views
Registered: ‎10-08-2013

VDMA S2MM how to change the Stream Data Width (auto)

Hello,

 

I´d like to change the S2MM stream data width on the vdma settings or get rid of the auto mode, I want 24bits instead 32bits, all my design is on video stream of 24bits but despite that is not changing automatically:

 

vdma.jpg

 

 

Is it possible to change manually?,for instance using a TCL command?

 

Thanks in advance.

 

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Xilinx Employee
Xilinx Employee
6,997 Views
Registered: ‎08-02-2011

Re: VDMA S2MM how to change the Stream Data Width (auto)

Hello,

 

This setting will change to the width of whatever is driving it automatically. When you validate design, do you get any errors about mismatched port sizes or anything like that? If not, then it is adapting fine and you don't need to worry about the grayed out GUI.

www.xilinx.com
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Contributor
Contributor
6,985 Views
Registered: ‎10-08-2013

Re: VDMA S2MM how to change the Stream Data Width (auto)

Hi bwiec,

Thanks for your reply.I'm not having errors.... I read that on the manual, it has to change automatically when validate design but it doesn't, despite there's a 24 bit bus connected to it. And I'm guessing is one of the problems I'm having for that I'd like to change manually and check it. Is not way to change it?
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Xilinx Employee
Xilinx Employee
6,979 Views
Registered: ‎08-02-2011

Re: VDMA S2MM how to change the Stream Data Width (auto)

Hi,

 

Oh okay. Yeah I've seen sometimes the grayed out value doesn't change, but it doesn't matter. It'll be correct if there are no errors.

 

Unfortunately, there is no way to manually set it.

www.xilinx.com
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Visitor
Visitor
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Registered: ‎09-11-2015

Re: VDMA S2MM how to change the Stream Data Width (auto)

I am having issues with the auto detect feature for S2MM AXI-S width.  I have a 16 bit signal going into the VDMA, and it is auto selecting 32 bit width.  When I validate the design, it does come up with critical warnings saying the ports are mismatched, and the tool doesn't change it to make it match.  To take it further, I decided to build a bit file anyway, and I can see that the data is being written into memory as 32 bit values, with the upper two bytes being zero.  This means to me that the design never updated the bit width through synthesis/implementation, and is zero padding the upper two bytes.  As there is no way to manually change the data width, how do I correct this issue?

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2,313 Views
Registered: ‎03-03-2017

Re: VDMA S2MM how to change the Stream Data Width (auto)

@bwiec / @florentw,

   Is there really no solution to this??   What if we manually go edit the verilog files?   I have a design I am working on where I cannot get the width to change, no matter what I try.   I tried disconnecting the individual lines which I had broken out and instead connected it to an AXI-stream bus that has a width of 119:0 but the tdata width on the VDMA will not change from 31:0.   Any suggestions?

 

vdma_width_problem.png

 

Thanks.

Tim

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Newbie
Newbie
1,212 Views
Registered: ‎03-16-2017

Re: VDMA S2MM how to change the Stream Data Width (auto)

Just chiming in to say I'm seeing the same exact error, and it's preventing my build from working correctly. The bus width is not autodetected correctly, and I get a critical warning about the bus width mismatch. Surely there has to be a way to work around this problem.

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Moderator
Moderator
1,185 Views
Registered: ‎11-09-2015

Re: VDMA S2MM how to change the Stream Data Width (auto)

Hi @tim_severance/ @nickcorvid,

You should able to change the configuration in the properies window when selecting the IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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