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Voyager
Voyager
676 Views
Registered: ‎05-30-2017

VDMA interlaced video write even field in even memory frame and odd field in odd memory frame

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Hello,

I configured VDMA write and read and 8 frame. And It works very well with progressive video. I would know if there is a way using xilinx IP with interlaced video to synchronize the writing so VDMA always writes even field in even memory  frame and odd field in odd memory frame. In this way I could use mm2s_frame_ptr_out[0] to know if I'm reading with VDMA an even or an odd field.

Thank you very much. 

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Moderator
Moderator
637 Views
Registered: ‎11-09-2015

Hi @pierlum ,

We discussed this topic recently:

https://forums.xilinx.com/t5/Video/Interlaced-Video-VMDA-and-VTG-Configuration/td-p/935614


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Moderator
Moderator
638 Views
Registered: ‎11-09-2015

Hi @pierlum ,

We discussed this topic recently:

https://forums.xilinx.com/t5/Video/Interlaced-Video-VMDA-and-VTG-Configuration/td-p/935614


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

Voyager
Voyager
622 Views
Registered: ‎05-30-2017

Hi @florentw ,

thank you very much for the topic. I'll read it.

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