VDMA interlaced video write even field in even memory frame and odd field in odd memory frame

[pierlum]

Hello,

I configured VDMA write and read and 8 frame. And It works very well with progressive video. I would know if there is a way using xilinx IP with interlaced video to synchronize the writing so VDMA always writes even field in even memory  frame and odd field in odd memory frame. In this way I could use mm2s_frame_ptr_out[0] to know if I'm reading with VDMA an even or an odd field.

Thank you very much. 

[florentw · Accepted solution]

Hi @pierlum ,

We discussed this topic recently:

https://forums.xilinx.com/t5/Video/Interlaced-Video-VMDA-and-VTG-Configuration/td-p/935614

[pierlum]

Hi @florentw ,

thank you very much for the topic. I'll read it.