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petercaddick
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Registered: ‎04-01-2019

VDMA internal error

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Hi

can some one please explain why I'm getting a VDMA internal error? See the attachments. S2MM_VDMACR status (0x34) = 15810. Bit 4 is set. When I look at the reason it says.

(a) HSIZE or VSIZE register were written zeros or
(b) Internal error received from helper core axi_datamover or
(c) Transferred frame size is lesser than programmed vsize (SOFEarlyErr).

In case (a) and/or (b) the channel stops (that is, the VDMACR.RS bit is set to 0 and remains cleared). To restart the channel, a soft or hard reset is required. In case (c), the channel does not stop or halt.

As you can see in the first screen capture (a) isn't the case (HSIZE & VSIZE are set). Also (c) isn't the case as no SOFFEarlyErr is flagged (bit 7 if status reg isn't set). So it has to be (b) but it says that the channel stops for (a) & (b) so it not (b) either (VDMA is still going). So what is the problem?

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vdma_internal_error_1.jpg
vdma_internal_error_2.jpg
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florentw
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Registered: ‎11-09-2015

Hi @petercaddick 

You have the bit 11 which is set to 1 wich means that you have a SOFLateErr error. So you will have less data than the programmed sized. So this is error c.

What is your frame size and the data width of the AXI4-Stream interface?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

HI @petercaddick 

Can you write 0xFFFFFFFF in the status register and try to read it again.

This will clear the register this way we can check if the error is consistent. This is something I am covering in my Video Series 25: Debugging issues on the AXI VDMA IP

Regards


Florent
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petercaddick
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Registered: ‎04-01-2019

@florentw The code already does this prior to reading the status register back.

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florentw
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Registered: ‎11-09-2015

Hi @petercaddick 

You have the bit 11 which is set to 1 wich means that you have a SOFLateErr error. So you will have less data than the programmed sized. So this is error c.

What is your frame size and the data width of the AXI4-Stream interface?

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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petercaddick
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Registered: ‎04-01-2019

@florentw. Thanks for the clarification. I was looking at the wrong status register. 

MM2S_VDMASR.jpg
S2MM_VDMASR.jpg
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florentw
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Registered: ‎11-09-2015

HI @petercaddick 


@petercaddick wrote:

@florentw. Thanks for the clarification. I was looking at the wrong status register.  It would have been helpful if you'd used the same registers for S2MM as MM2S.


[Florent] - This would make sense only if the VDMA always had read and write enable. But would make it more complicated for users when you have just read only or write only configuration.

Also, each interface is independent so I am not sure if it would really make sense.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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