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Adventurer
Adventurer
2,614 Views
Registered: ‎08-16-2017

VDMA vs Video FrameBuffer R/W IP Cores

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Going through the documentation of both IP core, it seems these two cores functionality is overlapping. In our video application we wish to just buffer and push the video into DDR ram. Is it fair to assume that FrameBuffer Write is all we need? When do we need a full VDMA core?

 

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Xilinx Employee
Xilinx Employee
2,867 Views
Registered: ‎08-02-2011
VDMA usage with MM2S disabled would be fine.

The Framebuffer read/write were written for VCU use cases in ZU+ devices because it expects specific format of the video data in memory.
www.xilinx.com

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Moderator
Moderator
2,549 Views
Registered: ‎11-09-2015
Hi @ziladdev,

Yes both core have the samd functionality. You could do write only with the VDMA also.
However I recommend to use the frame buffer as it seems to slowly replace the VDMA (better for Linux, better performance...)

Regards

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
2,508 Views
Registered: ‎11-09-2015

Hi @ziladdev,

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
2,487 Views
Registered: ‎08-16-2017

Thanks for the reply!

I have started using Video Frame Buffer instead of the VDMA, besides being a bit awkward. For instance, I had to pad the stream since for YUV422 it still expects 3x(8bits) components while my Video In to AXI4 spits outs 2x(8bits), this was clearly documented so no big deal.

 

One thing I noticed is that in terms of utilization it is using 2x DSP slices while VDMA uses none...I am wondering why would one need this for this function? I see the HLS logo on the actual block design and I was wondering if one had access to the (C/C++?) source code of the IP core ... (perhaps not!).

 

Anyways my design is quite heavy on the use of DSPs and It may happen that I will revert back to using VDMA...

 

Any views on this?

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Xilinx Employee
Xilinx Employee
2,868 Views
Registered: ‎08-02-2011
VDMA usage with MM2S disabled would be fine.

The Framebuffer read/write were written for VCU use cases in ZU+ devices because it expects specific format of the video data in memory.
www.xilinx.com

View solution in original post

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Participant
Participant
1,025 Views
Registered: ‎03-13-2016

Hi biwec,

So, Can i use Video FrameBuffer with Zynq-7000? If yes, can you show me how?

I trying to use Video FrameBuffer Read + Video Mixer to driven ALI3 10inch from Avnet, built with Petalinux, xilinx drm driver initialize ok but I can't see any /dev/fbx on root file system.

Can you give me some suggestion for this?

Thanks and best regard,

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-21-2020

I am pretty new to this concept . can someone explain me when to use VDMA and when to use frame buffer write ?

So , what i understood is that we use VDMA when we have to support live streaming interface. 

and Support VDMA when simply store data in to DDR memory . 

if someone has more details please share. 

 

regards,

Amit Verma

 

 

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Moderator
Moderator
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Registered: ‎11-09-2015

HI @eramitverma1 

You might want to refer to the following AR as this is covering it:

AR#72543: When should I use the VDMA and when should I use the Video Frame Buffer?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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