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Adventurer
Adventurer
1,575 Views
Registered: ‎03-08-2018

VPSS Initialization Issue

Hi,

 

In one of my project , I am using VPSS(Full Fledged) for scaling video. I used the following functions to init the IP core in SDK.

 

XVprocSs_SetFrameBufBaseaddr(pVprocss,DDR);

VprocSsConfigPtr = XVprocSs_LookupConfig(XVPROCSS_ID);
if(VprocSsConfigPtr == NULL)
{
xil_printf("ERR:: VprocSs IP not found\r\n");
}
Status = XVprocSs_CfgInitialize(pVprocss, VprocSsConfigPtr,VprocSsConfigPtr->BaseAddress);
if(Status != XST_SUCCESS)
{
xil_printf("VSSP init failed\n\r");
}
else
{
xil_printf("VSSP init passed\n\r");
}

To check function initialization , i am using Debugger in SDK.  The first two function is executed without any issue. when control comes into XVprocSs_CfgInitialize(pVprocss, VprocSsConfigPtr,VprocSsConfigPtr->BaseAddress), it stuck at 

if(InstancePtr->RouterPtr) {
if(XVprocSs_SubcoreInitRouter(InstancePtr) != XST_SUCCESS) {
return(XST_FAILURE);
}
}

 

I have attached the screen shot of debugging window. Please help me to debug it.

 

Thanks 

Kannan

 

vpss.png
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6 Replies
Adventurer
Adventurer
1,562 Views
Registered: ‎03-08-2018

The control stuck at this function

void XAxisScr_MiPortDisableAll(XAxis_Switch *InstancePtr)
{
u32 MiPortAddr;
u8 Index;

/* Verify argument. */
Xil_AssertVoid(InstancePtr != NULL);

for (Index = 0; Index < InstancePtr->Config.MaxNumMI; Index++) {

/* Calculate MI port address of which to be enabled */
MiPortAddr = XAXIS_SCR_MI_MUX_START_OFFSET + 4 * Index;

XAxisScr_WriteReg(InstancePtr->Config.BaseAddress, MiPortAddr,
XAXIS_SCR_MI_X_DISABLE_MASK);
}
}
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Adventurer
Adventurer
1,519 Views
Registered: ‎03-08-2018

Hi,

 

Is there any solutions for that?

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Moderator
Moderator
1,470 Views
Registered: ‎11-09-2015

Hi @kannan,

 

Could you start with the example design for the VPSS?

 

The application example design is really helpful as the VPSS requires steps to be done in a specific order.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
1,445 Views
Registered: ‎03-08-2018

Hi florentw,

 

Thank for your response.

 

I have no issue with example design.

 

I am getting timing violation in my design which is related to Video Processing Subsystem and AXI Interconnect.

 

Could it be possible of Initialization issue?

 

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Moderator
Moderator
1,439 Views
Registered: ‎11-09-2015

HI @kannan,

 

Yes you have a big timing violation so it might be the root cause. You should try to fix it first.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,148 Views
Registered: ‎11-09-2015

HI @kannan,

 

Do you have any updates on this?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" buton below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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