Video Beginner Series 6: From AXI4-Stream to Native Video

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Introduction

This Video Beginner Series 6 shows how convert AXI4-Stream video data to Native Video Signals.

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Summary

1. Xilinx VTC and AXI4-Stream to Video Out IPs

2. Tutorial - From AXI4-Stream to Native Video

3. What next?

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Xilinx VTC and AXI4-Stream to Video Out IPs

 

The Xilinx LogiCORE™ IP Video Timing Controller (VTC) core is a general purpose video timing generator and detector. It can generates/detects video timing signals (hsync, vsync, hblank, vblank, active_video) for frame sizes up to 8192 x 8192.

The Xilinx VTC IP as generator can use preset frame sizes or can include an AXI4-Lite interface to be reprogrammed while running.

For information on the Xilinx LogiCORE™ IP Video Timing Controller core, refer to PG016.

The Xilinx LogiCORE™ IP AXI4-Stream to Video Out core is designed to provide a bridge between AXI4-Stream video data to native video.

For more information on the Xilinx LogiCORE™ IP AXI4-Stream to Video Out core, refer to PG044.

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Tutorial - From AXI4-Stream to Native Video

Note: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

Build the Vivado project

1. Download the tutorial files and unzip the folder
   
   
2. Open Vivado 2018.1
   
   
3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0006)
   
   
4. In the tcl console, source the script tcl (source ./create_proj.tcl)
   Note: A valid license for the Test Pattern Generator is required to build the design.

From AXI4-Stream Video Data to Native Video

5. Open the Block Design (BD) if not opened
   
   
6. To convert the AXI4-Stream video output from the TPG IP to native video, add an AXI4-Stream to Video Out IP
   1. Right click on the BD and click Add IP…
      
      
      
   2. Search for video out and double click on AXI4-Stream to Video Out
      
      

7. Connect the video_in input of the AXI4-Stream to Video Out to the m_axis_video output from the TPG
   
   
8. Connect the aclk and aresetn inputs of the AXI4-Stream to Video Out to the aclk_40MHz and aresetn_0
   
9. Expend the interface vio_io_out of the AXI4-Stream to Video Out by clicking on the “+” and connect the sub-signals to the corresponding BD outputs
   

Generating the timing signals

The AXI4-Stream to Video Out IP does not generate the timing signals. It designed to be used in parallel with a Video Timing Controller (VTC) IP configured as generator.

10. Add a Video Timing Controller to the design
    1. Right-click on the BD and click Add IP…
    2. Search for timing and double click on Video Timing Controller to add the IP

For this tutorial, we will use a fixed resolution for the TPG (and the output frame) of 800 x 600 @60Hz.

11. Double click on the Video Timing Controller to configure it
    1. In the page Detection/Generation
       • Disable Include AXI4-Lite Interface
       • Disable Enable Detection
         
         

2. Go to the Default/Constant page and select 800x600p for Video Mode and click OK
   
   

12. Connect clk and resetn inputs of the VTC to aclk_40MHz and aresetn_0 BD inputs and connect the vtiming_out VTC output to the vtiming_in AXI4-Stream to Video Out input.
    

13. Connect the vtg_ce output from the AXI4-Stream to Video Out to to the gen_clken input of the VTC
    
    
    
14. Verify the Block Design (Tools > Validate Design)
    
    
15. Save the BD
    
    

Run the simulation

16. Run the behavioral simulation for 150 ms.
    
    
17. Go to a simulation time around time 90ms. You can see that the AXI4-Stream is getting locked (rising edge of the locked output). This means it is ready to convert the AXI4-Stream video data to Native Video
    
    
18. You can see that after 107ms the AXI4-Stream to Video Out starts to output Native Video
    
19. Close the simulation and Vivado

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