Video Beginner Series 7: How does the AXI4-Stream to Video Out IP work?

[florentw]

Introduction

This Video Beginner Series 7 helps you understand how the Xilinx AXI4-Stream to Video Out IP is working.

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Summary

1. Understanding the AXI4-Stream to Video Out

2. AXI4S to Video Out IP - Detail on the Output Synchronizer

3. Tutorial - Video AXI4-Stream to video Out in Slave timing mode

4. What next?

[florentw]

Understanding the AXI4-Stream to Video Out

The figure 1-1 of PG044 shows a diagram of the AXI4-Stream to Video out core.

We can divide the core in 3 parts:

• a data part (in red below)
• a timing signals part (in green)
• a synchronization part (in orange)

Data Part

The data are going through a FIFO and are then formatted (to follow the AXI4-Stream encoding for Xilinx Video IPs as per UG934). The AXI4-Stream starts to output the data only when it gets the locked signal from the synchronizer.

Timing Signals Part

The timing signals are only going through the AXI4-Stream to Video Out from the VTC without any alteration. The AXI4-Stream starts to output the timing signals only when it gets the locked signal from the synchronizer.

Synchronization Part

The Output Synchronizer block takes the frame boundary information signals from the AXI4-Stream (Start Of Frame (SOF - carried by tuser) and End Of Line (EOL - carried by tlast)) and the timing signals from the VTC IP as input to synchronize the data and the timing signals. Depending on the timing mode, Master or Slave, it will control the VTC (using vid_gen_ce) or the internal FIFO to achieve the synchronization.

A detail explanation of the Timing mode is provided in the PG044, Chapter 3: Designing with the Core, Timing mode section.

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AXI4S to Video Out IP - Detail on the Output Synchronizer

The figure 3-10 from the PG044 shows how the synchronizer is working:

The AXI4-Stream to video out will first enter in a Coarse Alignment phase (also called initial Alignment), then in a Fine Alignment before getting locked.

A detail of the Corse Alignment and Fine Alignment is provided in PG044.

The current phase can be followed by looking at the status output of the AXI4-Stream to Video Out

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Tutorial - From AXI4-Stream to Native Video

Note: This tutorial is intended to be used only with Vivado 2018.1 and only in simulation

Build the Vivado project

1. Download the tutorial files and unzip the folder
   
   
2. Open Vivado 2018.1
   
   
3. In the tcl console, cd into the unzipped directory (cd <path>/XVES_0007)
   
   
4. In the tcl console, source the script tcl (source ./create_proj.tcl)

Note 1: A valid license for the Test Pattern Generator is required to build the design.
Note 2: The design is the same as the Video Beginner 6.

5. Double click on the AXI4-Stream to Video Out IP to open its configuration GUI

 

• We can see that the Timing Mode is set as Slave. This means that the AXI4-Stream to Video Out IP will control the Video Timing Controller configured as Generator (commonly called VTG) using the vtg_ce output port in order to synchronize the timing signal with the incoming data stream.
  
  
• We can also see a parameter Hysteresis Level (or fill level). This parameter indicates how many samples (i.e. pixels) the IP should wait, when the data stream and timing signals are synchronized, before outputting data. In this case, and by default for the IP, it is configured to 12.

Understanding the AXI4-Stream to Video Out in Slave Timing Mode

6. Launch the behavioral simulation and run it for 150ms.
   
   
7. At simulation time 16.579ms we can see that the AXI4-Stream to video out IP set vtc_ce to ‘0’ to keep the VTC on hold, just after the vsync/vblank (i.e. start of frame)

 

8. We can see that the value on the status output at this simulation time is 0x000c0002. The bit 1 of status is high, indicating that the AXI4-Stream to Video Out IP enters in the Coarse Align Phase
   
   
9. At simulation time 24.181ms, the vtc_ce the AXI4-Stream to Video Out IP set vtc_ce to back to ‘1’ to continue the timing.
   
   Q1. Check the AXI4-Stream signals. What signals are happening before the AXI4-Stream to video out IP set vtc_ce to back to ‘1’?
   
   Q2. Which AXI4-Stream signal “trigger” the AXI4-Stream to Video Out IP to set vtc_ce to ‘1’?
   
   
10. We can see that the value on the status output at this simulation time is 0x000c0186. The bit 7 of status is high, indicating that the AXI4-Stream to Video Out IP is in the Fine Align Phase
    
    
11. At simulation time 90.4987ms, the AXI4-Stream to Video Out IP is getting locked and starts outputting native video after one frame (at 106.33ms)

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