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kaesar
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Contributor
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Registered: ‎01-09-2017

Video Frame Buffer IP

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Hi, I am working on a video project using Video Frame Buffer IP, I have a question about the AXI4-Lite control interfaces, my DDR address is 64bit, the data with of AXI4-Lite control interfaces is 32 bit, the address of the control register of the frame buffer start address is 0x0030, if my DDR memory reference address is 0x00000001_00000000, how should I set the frame address control register? Write 0x00000000 to 0x0030, then 0x00000001 to 0x0034?

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florentw
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Registered: ‎11-09-2015

HI @kaesar

The flow for the example design mentioned in pg278 is only working for the KC705.

For ZCU102/ZCU104/ZCU106, you need to import the example application from the BSP

I will publish a Video series about the Video Frame buffer example design next wednesday on the Design and Debug Techniques blog. Keep an eye on it (but it will be based on 2019.2 and vitis) ;)

If you are using SDK:

  1. export the hdf
  2. Create a Board Support Package (BSP)
  3. In the mss file create in the bsp, find the line for the video frame buffer and click import example

This will be updated in the next version of the PG278

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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ashokkum
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Registered: ‎04-09-2019

Hello @kaesar ,

Please go through the example design addressed in the chapter-5 of the PG278 and try to reproduce this at your end. In this example design DDR3 was used to store the data. So, by refferring the example design you will get a clear picture about the address and data processing of the DDR.

With Regards,

Ashok

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kaesar
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Registered: ‎01-09-2017

i have created a synthesizable example design follows the PG278(V2.1, VIVADO 2019.1), but there are a lot of Compile Errors with SDK(undefine values and files). where can i have a verified project.

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ashokkum
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Moderator
514 Views
Registered: ‎04-09-2019

Hello @kaesar ,

I need to reproduce the example design at my end. So, Please give me some time I will update you on this as soon as possible.

With Regards,

Ashok.

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florentw
Moderator
Moderator
491 Views
Registered: ‎11-09-2015

HI @kaesar

The flow for the example design mentioned in pg278 is only working for the KC705.

For ZCU102/ZCU104/ZCU106, you need to import the example application from the BSP

I will publish a Video series about the Video Frame buffer example design next wednesday on the Design and Debug Techniques blog. Keep an eye on it (but it will be based on 2019.2 and vitis) ;)

If you are using SDK:

  1. export the hdf
  2. Create a Board Support Package (BSP)
  3. In the mss file create in the bsp, find the line for the video frame buffer and click import example

This will be updated in the next version of the PG278

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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