cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
253 Views
Registered: ‎11-13-2017

Video PHY Controller: DisplayPort 1.4 setting

Jump to solution

Hi,

We are developing a DisplayPort 1.4 RX unit using MPSoC XCZU19EG. The design is based on the ZCU102 DP RX only example (dp_rx_subsystem_0_ex). Right now, there is an issue on RXRESETDONE. Host PC detects Xilinx DP. But it is always inactive. Looking at VPHY register, RXRESETDONE is always 0.

So I am looking into the Video PHY. In PG230 section "DisplayPort Clocking", Reference Clock for DisplayPort 1.2 and DisplayPort 1.4 are described. However there is no setting for 1.2 / 1.4 on the Video PHY IP. (screenshot attached)

How can I set the Video PHY for DisplayPort 1.4?

Thank you,
--fuji

 

Screenshot.png

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
195 Views
Registered: ‎10-04-2017

Hi @yfuji38,

 

There is no need to set the V-PHY for DP1.2 DP1.4. 

The PHY handles the transceiver specific settings for the DP IP. The differences in the specifications are handled by the attached DisplayPort IP.

 

However, please make sure you are setting the Maximum line rate correctly. If you do not set this correctly, you will run into problems.

 

Stepping back and looking at your error. If RXRESETDONE is not going high, it is likely an interface connection is not correct. Please check your clocks and resets. Specifically, make sure your RX Ref Clock Selection is correctly pinned out to a valid clock and that you are not holding the core in reset.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

0 Kudos
2 Replies
Highlighted
Moderator
Moderator
196 Views
Registered: ‎10-04-2017

Hi @yfuji38,

 

There is no need to set the V-PHY for DP1.2 DP1.4. 

The PHY handles the transceiver specific settings for the DP IP. The differences in the specifications are handled by the attached DisplayPort IP.

 

However, please make sure you are setting the Maximum line rate correctly. If you do not set this correctly, you will run into problems.

 

Stepping back and looking at your error. If RXRESETDONE is not going high, it is likely an interface connection is not correct. Please check your clocks and resets. Specifically, make sure your RX Ref Clock Selection is correctly pinned out to a valid clock and that you are not holding the core in reset.

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

0 Kudos
Highlighted
Observer
Observer
173 Views
Registered: ‎11-13-2017

Hi @samk,

Thank you for your reply.

Seems like the Video PHY Controller must be attached to the DisplayPort subsystem IP. It would be better not to try using the the Video PHY Controller only.

Actually, the RXRESETDONE issue was caused by wrong Ref Clock selection. I had to modify the sample source code to change REFCLKSEL settings. Now the Rx reset is working.

Thank you!

 

0 Kudos