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Observer
Observer
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Registered: ‎06-25-2019

Video Phy Controller MMCM

I am trying to create an HDMI TX design. I had used the HDMI example design as a reference. I am using CPLL for TX PLL. I have attached the screenshot of the Video Phy Controller configuration and HDMI design. My aim is to transmit a video of 1080p60 resolution at 12BPC and 4PPC so I configured the external clock source to generate vid_phy input reference clock at frequency 148.5MHz.

In the Video Phy constraints file for clocks(vcu_example_vid_phy_controller_0_0_ooc_fixed.xdc)  the input clock to the port 'mgtrefclk0_pad_p_in' is configured for 297MHz

create_clock -name vcu_example_vid_phy_controller_0_0_vid_phy_axi4lite_aclk -period 10 [get_ports vid_phy_axi4lite_aclk]
create_clock -name vcu_example_vid_phy_controller_0_0_vid_phy_tx_axi4s_aclk -period 6.734 [get_ports vid_phy_tx_axi4s_aclk]
create_clock -name vcu_example_vid_phy_controller_0_0_vid_phy_sb_aclk -period 10 [get_ports vid_phy_sb_aclk]

# GTH, GTY
create_clock -name vcu_example_vid_phy_controller_0_0_drpclk -period 10 [get_ports drpclk]


create_clock -name vcu_example_vid_phy_controller_0_0_mgtrefclk0_pad_p_in -period 3.367 [get_ports mgtrefclk0_pad_p_in]


During implementation, I got the following critical warning. What could be the reason for this warning?

[DRC AVAL-46] v7v8_mmcm_fvco_rule1: The current computed target frequency, FVCO, is out of range for cell Project_top/project_i/hdmi_path/vid_phy_controller_0/inst/gt_usrclk_source_inst/tx_mmcm.txoutclk_mmcm0_i/mmcm_adv_inst. The computed FVCO is 594.001 MHz. The valid FVCO range for speed grade -1 is 800MHz to 1600MHz. The cell attribute values used to compute FVCO are CLKFBOUT_MULT_F = 4.000, CLKIN1_PERIOD = 6.73400, and DIVCLK_DIVIDE = 1 (FVCO = 1000 * CLKFBOUT_MULT_F/(CLKIN1_PERIOD * DIVCLK_DIVIDE)).
This violation may be corrected by:
1. The timer uses timing constraints for clock period or clock frequency that affect CLKIN1 to set cell attribute CLKIN1_PERIOD, over-riding any previous value. This may already be in place and, if so this violation will be resolved once Timing is run. Otherwise, consider modifying timing constraints to adjust the CLKIN1_PERIOD and bring FVCO into the allowed range.
2. In the absence of timing constraints that affect CLKIN1, consider modifying the cell CLKIN1_PERIOD to bring FVCO into the allowed range.
3. If CLKIN1_PERIOD is satisfactory, modify the CLKFBOUT_MULT_F or DIVCLK_DIVIDE cell attributes to bring FVCO into the allowed range.
4. The MMCM configuration may be dynamically modified by use of DRP which is recognized by an ACTIVE signal on DCLK pin.

And based on what calculation did the input reference clock through port 'mgtrefclk0_pad_p_in' is configured for 297MHz?

'vid_phy_sb_aclk', 'vid_phy_axi4lite_aclk', and 'drpclk' are configured for 100MHz

Thanks in advance.

Tags (2)
Vid phy controller config_r19.jpg
HDMI path_2.jpg
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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @shahan.a,

 

The Video PHY's MMCM is configured dynamically at runtime using DRP ports.

What this is saying is that the default Multiply and Divide of the MMCM is not correct for the fabric that you are using.  This will be corrected at runtime by the VPSS/HDMI drivers.


For most HDMI use-cases 4Kp30 may be required. In this case, the clock is 297MHz. Because we want the HDMI system to be timed for the worst-case timing we use the fastest clock for the system.

I believe if you define your clock as 297MHz for synthesis this error will go away. **As you are only doing 1080p60 and will not need 297MHz, I believe if you leave your clock at 148.5 you can ignore this warning as it will be resolved at runtime.

-Sam

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Xilinx Video Design Hub
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