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Observer
Observer
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Registered: ‎11-11-2019

Video Timing Controller

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Dear community,

I have run into some trouble with the Video Timing Generator IP (6.1)

I am trying to generate standart timing pulses for 1080p resolution. This means that HSYNC should be active for 44 pixels and VSYNC should be active for 5 lines. 

My problem is that HSYNC stays active only for 1 pixel and VSYNC only for 1 line. HBLANK and VBLANK seems to OK (these are comming from "Video In to
AXI4-Stream v4.0" IP Core). The two screenshots are the VTC IP settings and the third one from ILA (showing to lines of video) .

Anybody have an idea what could be resetting the SYNCs?

Best Regards

 

TC01.png
TC02.png
TC03.png
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Observer
Observer
384 Views
Registered: ‎11-11-2019

Hello Florent,

at the end it came out that it was a general design timing issue. I replaced custom VHDL serializers used for the LCD LVDS output with the OSERDES primitives to resolve the timing issues.

 

Best Regards

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Moderator
Moderator
471 Views
Registered: ‎11-09-2015

HI @sa_fpga 

The generation part is sync to the detection part. So this might be were you need to look at.

Are the signals my_tc* the timing signals which are going into the VTC detector? Looking at the active video signals, it does not seems to be low during blanking period. This is not an expected behaviour so I am wondering if this could cause the hsync behaviour?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Observer
Observer
449 Views
Registered: ‎11-11-2019

Dear Florent,

thank you for the hint. If I configure the VTC free running without the detection part everything is ok, so the detection is not working.

The my_tc* signals are the output of the VTC. The input of the VTC are the my_vtd* signals. These are comming from the "SDI RX Bridge IP".

 

 

 

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Moderator
Moderator
446 Views
Registered: ‎11-09-2015

Hi @sa_fpga 

You might want to look at the intc_if output from the VTC, to see if you see any error flagged from the detection part


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Highlighted
Observer
Observer
385 Views
Registered: ‎11-11-2019

Hello Florent,

at the end it came out that it was a general design timing issue. I replaced custom VHDL serializers used for the LCD LVDS output with the OSERDES primitives to resolve the timing issues.

 

Best Regards

View solution in original post

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Moderator
Moderator
366 Views
Registered: ‎11-09-2015

Hi @sa_fpga 

Great. Good to hear that you have found the issue.

Could you kindly mark your last reply as accepted solution to close the topic?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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