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Visitor
Visitor
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Registered: ‎07-26-2018

Video VTC and VDMA

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Hello, I'm trying to capture video using a custom screen size which is roughly 564x1218 pixels. I have vsync, hsync, display_enable and a pixel clock running at 112MHz. I'm trying to use the Video In to AXI4-Stream -> VDMA -> AXI4-S to Video Out data path with this custom video input. I want to output this to 1080p HDMI (148.5MHz pixel clk). So in the case I have asynchronous clocks for writing into VDMA and reading out and the screen sizes are different. My questions are:

1) Is this even possible using the built in Video In to AXI4-Stream and VDMA? Or do I have to write a custom HDL for this DMA controller?

2) If it is possible, how should it be setup? Since the clock rate out is higher than in it should be doable from a bandwidth standpoint but how can these built in AXI4-Stream blocks be configured to work in this case?

Any info or example that uses asynchronous video in and out clockswould be helpful. Thanks.

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Moderator
Moderator
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Registered: ‎11-09-2015

@jyingling wrote:

Hello, I'm trying to capture video using a custom screen size which is roughly 564x1218 pixels. I have vsync, hsync, display_enable and a pixel clock running at 112MHz. I'm trying to use the Video In to AXI4-Stream -> VDMA -> AXI4-S to Video Out data path with this custom video input. I want to output this to 1080p HDMI (148.5MHz pixel clk). So in the case I have asynchronous clocks for writing into VDMA and reading out and the screen sizes are different. My questions are:

1) Is this even possible using the built in Video In to AXI4-Stream and VDMA? Or do I have to write a custom HDL for this DMA controller?

[Florent] - Yes this is possible with the Videio In to AXI4S and VDMA

2) If it is possible, how should it be setup? Since the clock rate out is higher than in it should be doable from a bandwidth standpoint but how can these built in AXI4-Stream blocks be configured to work in this case?

[Florent] - The clock is not an issue here. The VDMA will do the clock crossing for you. And as long as you are in AXI4-Stream interface you are not talking about video timing anymore. Thus the clock could even be the same on both side of the VDMA. But you need to take care of overflows / underflows.

The thing you need to think about is if you want to scale or just crop the picture when doing the resolution change.

Any info or example that uses asynchronous video in and out clockswould be helpful. Thanks.

 

Will the video in to axi4-stream accept non-standard screen resolutions? In my case 564x2436 pixels at 112MHz. I want to be able to turn this into a axi4-stream and I'm having trouble doing so. I'm trying to use the VTC to generate my syncs but it is failing to output a vsync.

[Florent] - It might work with some non-standard resolution but the timing still need to be meaningful (the vsync and hsync needs to happen at the correct time). I have seen some video timing not detected by the vtc but moving slightly the vsync and hsync helped to solve. Just look at the status output of the VTC. It should guide you if the VTC is not working.


Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Visitor
Visitor
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Registered: ‎07-26-2018

Perhaps a better way to ask this question is:

Will the video in to axi4-stream accept non-standard screen resolutions? In my case 564x2436 pixels at 112MHz. I want to be able to turn this into a axi4-stream and I'm having trouble doing so. I'm trying to use the VTC to generate my syncs but it is failing to output a vsync.

any help is appreciated. thanks.

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Teacher
Teacher
1,004 Views
Registered: ‎06-16-2013

Hi @jyingling

 

Does your design have an external DRAM as frame buffer ?

If no, it is difficulty to archive it.

It might be success, if you have a lot of knowledge.

So I suggest using frame buffer.

 

Best regards,

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Moderator
Moderator
971 Views
Registered: ‎11-09-2015

@jyingling wrote:

Hello, I'm trying to capture video using a custom screen size which is roughly 564x1218 pixels. I have vsync, hsync, display_enable and a pixel clock running at 112MHz. I'm trying to use the Video In to AXI4-Stream -> VDMA -> AXI4-S to Video Out data path with this custom video input. I want to output this to 1080p HDMI (148.5MHz pixel clk). So in the case I have asynchronous clocks for writing into VDMA and reading out and the screen sizes are different. My questions are:

1) Is this even possible using the built in Video In to AXI4-Stream and VDMA? Or do I have to write a custom HDL for this DMA controller?

[Florent] - Yes this is possible with the Videio In to AXI4S and VDMA

2) If it is possible, how should it be setup? Since the clock rate out is higher than in it should be doable from a bandwidth standpoint but how can these built in AXI4-Stream blocks be configured to work in this case?

[Florent] - The clock is not an issue here. The VDMA will do the clock crossing for you. And as long as you are in AXI4-Stream interface you are not talking about video timing anymore. Thus the clock could even be the same on both side of the VDMA. But you need to take care of overflows / underflows.

The thing you need to think about is if you want to scale or just crop the picture when doing the resolution change.

Any info or example that uses asynchronous video in and out clockswould be helpful. Thanks.

 

Will the video in to axi4-stream accept non-standard screen resolutions? In my case 564x2436 pixels at 112MHz. I want to be able to turn this into a axi4-stream and I'm having trouble doing so. I'm trying to use the VTC to generate my syncs but it is failing to output a vsync.

[Florent] - It might work with some non-standard resolution but the timing still need to be meaningful (the vsync and hsync needs to happen at the correct time). I have seen some video timing not detected by the vtc but moving slightly the vsync and hsync helped to solve. Just look at the status output of the VTC. It should guide you if the VTC is not working.


Hope that helps,

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Visitor
Visitor
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Registered: ‎07-26-2018

Thanks, I will try this. I am using with external memory and using triple frame buffer. It is almost working but I need to get the vertical sync synchronized because as you mention the VTC needs it setup just right. Thanks for your responses.

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