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Adventurer
Adventurer
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Registered: ‎11-09-2016

Video processing in PS using VDMA

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Hi,

I did some operations using VDMA like video cropping, color patterns on screen or displaying real video on screen. I know well using Xilinx IPs. 

But these operations only include frame buffer addressing or readdressing, not any math operations(e.g. edge detection of input video)

Since data from camera on DRAM accesible from CPU, i want to process every new camera frame and write back to the DRAM. As for the screen can reads and shows new processed(e.g. blurred) frames instead of original camera frames. 

Is it possible to do video operations on PS side not AXIS path in PL?

Thanks

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Moderator
Moderator
467 Views
Registered: ‎11-09-2015

Hi @berker_atel 


1- When a S2MM IRQ is got which register should be read to learn the frame buffer which written last from VDMA. 

PARK_PTR_REG[24:28] = WrFrmStore ?

[Florent] - Well in your case, you should probably control everything from the processor. So your application should keep track of what it 

2- When a S2MM IRQ is got,of course i can learn last frame buffer number and i can apply algorithms on the data in PS, but what is the best time to write the data again on DDR? (I mean e.g. blurred image data here) Note: Why i write again? Beacuse i want to display blurred images. 

[Florent]  - It depends on how many frame buffer you have. With 6 frame buffers you can do everything in parallele. Basically you do a triple frame buffer use case between the VDMA write and PS read and then a triple frame buffer between the PS write and VDMA read.

3- If i write the blurred data when operation done, it can coincide the reading time by MM2S channel. When to refresh DDR with new data? I don't want to disrupt the well working frame buffer mechanism VDMA itself?

[Florent]  - Refer to my previous answer

 

 

//VGA
void MM2S_ISR(void *CallbackRef)
{

u32 cur_mm2sCR = Xil_In32(VDMA_BASE_ADDR+4);
Xil_Out32(VDMA_BASE_ADDR+4,cur_mm2sCR|0x00001000); //Clear INT
MM2S_Flag=1;

}

//CAM
void S2MM_ISR(void *CallbackRef)
{

u32 cur_s2mmCR = Xil_In32(VDMA_BASE_ADDR+52);
Xil_Out32(VDMA_BASE_ADDR+52,cur_s2mmCR|0x00001000); //Clear INT
S2MM_Flag=1;

}

 

"How to avoid this circumstances?"

frames.png

[Florent]  - Same, you can avoid this by using 6 frame buffers

4- What is the meaning of Frame delay in MM2S FRMDELAY_STRIDE[24:28] Register? For a camera->screen passthrough application, current frame on the screen, in fact before 4 frames ago camera data in case 4 frames delay? This mean we have more time for processing? Is it true? 

[Florent]  - This is not exactly true. Because if your PS is not as fast as your input you will still loose frame. It can give you some latency if you want to work on multiple frames at the same time

Best Regards


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎11-09-2016

Hi,

@bwiec i've seen many questions before you helped about dma and vdma. Can you help if you have time.

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @berker_atel 

 

I'm sure that it's hard to explain detail without your design.

But, I suggest you to read Xilinx Video Series 24, 25, 26 to understand how to use VDMA, first.

 

Best regards,

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Adventurer
Adventurer
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Registered: ‎11-09-2016

Thanks for your advice. 

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Moderator
Moderator
500 Views
Registered: ‎11-09-2015

Hi @berker_atel 

You can access the memory from the PS, then you can do your operations.

You just need to handle what frame buffers will be read and written by the VDMA to make sure you are not reading/writting on the same frame buffer with the PS


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
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Registered: ‎11-09-2016

Hi @florentw 

I have extra questions, i appreciate if you answer. 

1- When a S2MM IRQ is got which register should be read to learn the frame buffer which written last from VDMA. 

PARK_PTR_REG[24:28] = WrFrmStore ?

2- When a S2MM IRQ is got,of course i can learn last frame buffer number and i can apply algorithms on the data in PS, but what is the best time to write the data again on DDR? (I mean e.g. blurred image data here) Note: Why i write again? Beacuse i want to display blurred images. 

3- If i write the blurred data when operation done, it can coincide the reading time by MM2S channel. When to refresh DDR with new data? I don't want to disrupt the well working frame buffer mechanism VDMA itself?

while(1)
{
if ( S2MM_Flag == 1)
{
S2MM_Flag=0;
//Read last written frame to an array 

//Do operations on the array

//Write the new array to DDR here?

}

if (MM2S_Flag == 1)
{
MM2S_Flag=0;
//Write the new array to DDR  OR here?

}

}

 

 

//VGA
void MM2S_ISR(void *CallbackRef)
{

u32 cur_mm2sCR = Xil_In32(VDMA_BASE_ADDR+4);
Xil_Out32(VDMA_BASE_ADDR+4,cur_mm2sCR|0x00001000); //Clear INT
MM2S_Flag=1;

}

//CAM
void S2MM_ISR(void *CallbackRef)
{

u32 cur_s2mmCR = Xil_In32(VDMA_BASE_ADDR+52);
Xil_Out32(VDMA_BASE_ADDR+52,cur_s2mmCR|0x00001000); //Clear INT
S2MM_Flag=1;

}

 

"How to avoid this circumstances?"

frames.png

4- What is the meaning of Frame delay in MM2S FRMDELAY_STRIDE[24:28] Register? For a camera->screen passthrough application, current frame on the screen, in fact before 4 frames ago camera data in case 4 frames delay? This mean we have more time for processing? Is it true? 

Best Regards

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Highlighted
Moderator
Moderator
468 Views
Registered: ‎11-09-2015

Hi @berker_atel 


1- When a S2MM IRQ is got which register should be read to learn the frame buffer which written last from VDMA. 

PARK_PTR_REG[24:28] = WrFrmStore ?

[Florent] - Well in your case, you should probably control everything from the processor. So your application should keep track of what it 

2- When a S2MM IRQ is got,of course i can learn last frame buffer number and i can apply algorithms on the data in PS, but what is the best time to write the data again on DDR? (I mean e.g. blurred image data here) Note: Why i write again? Beacuse i want to display blurred images. 

[Florent]  - It depends on how many frame buffer you have. With 6 frame buffers you can do everything in parallele. Basically you do a triple frame buffer use case between the VDMA write and PS read and then a triple frame buffer between the PS write and VDMA read.

3- If i write the blurred data when operation done, it can coincide the reading time by MM2S channel. When to refresh DDR with new data? I don't want to disrupt the well working frame buffer mechanism VDMA itself?

[Florent]  - Refer to my previous answer

 

 

//VGA
void MM2S_ISR(void *CallbackRef)
{

u32 cur_mm2sCR = Xil_In32(VDMA_BASE_ADDR+4);
Xil_Out32(VDMA_BASE_ADDR+4,cur_mm2sCR|0x00001000); //Clear INT
MM2S_Flag=1;

}

//CAM
void S2MM_ISR(void *CallbackRef)
{

u32 cur_s2mmCR = Xil_In32(VDMA_BASE_ADDR+52);
Xil_Out32(VDMA_BASE_ADDR+52,cur_s2mmCR|0x00001000); //Clear INT
S2MM_Flag=1;

}

 

"How to avoid this circumstances?"

frames.png

[Florent]  - Same, you can avoid this by using 6 frame buffers

4- What is the meaning of Frame delay in MM2S FRMDELAY_STRIDE[24:28] Register? For a camera->screen passthrough application, current frame on the screen, in fact before 4 frames ago camera data in case 4 frames delay? This mean we have more time for processing? Is it true? 

[Florent]  - This is not exactly true. Because if your PS is not as fast as your input you will still loose frame. It can give you some latency if you want to work on multiple frames at the same time

Best Regards


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Moderator
Moderator
420 Views
Registered: ‎11-21-2018

Hi @berker_atel 

If your question is answered or your issue is solved, please kindly mark the response which helped as a solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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