01-28-2019 04:40 PM
I have a KCU105 EVM and DP1.4 FMC card. I was able to have tgp and displayport IP working and get dptx working.
In our application, we would like to have the test pattern to do the following:
1. Support super frame: for example, to generate 1600x600 image then we can split it left to right into two 800x600 image. To generate 1600x600 image, the pattern needs to be different for first 800 vs last 800 pixels for each line.
2. Alternating pixels: for example, to generate 1600x600 image, each line, pixel value is alternating (red, green, red, green... for example), then this output from FPGA can be split in even-odd vertical lines using our application.
For TPG, only color bar can help with different left-right image. No alternating pixel available. A more ideal way is for FPGA to take any customer image as input and use it to generate video out. Is it possible? If yes, could the image file be loaded through SDK? or how is it sent to FPGA as input?
What IP blocks do I need to make it happen?
BTW, I also ordered ZCU102 EVM. Suggetions on either KCU105 or ZCU102 works for me.
01-29-2019 10:04 PM
I guess you consider how to display your test patterns for 3D or VR.
If yes, I suggest the following 3rd party IP.
Would you refer it ?
Also, if you can implement DRAM controller by MIG as a frame buffer controller, VDMA IP and Microblaze and use ex. linux, I suggest using an application for test pattern on linux, too.
01-29-2019 10:42 PM
Thanks a lot for the suggestions.
I'm using FPGA as a test source generator. My product will use the test pattern and perform frame splitting. Therefore I need FPGA to generate videos with super-frames (one frame contains multiple standard video frame).
The suggested IP seem to be able to perform scaling, not sure if it can generate super-frame.
I may not need a IP for superframe generation. I can use other tool to generate a desired image. As long as I can put a superframe image into memory and use that test pattern for video stream, that'll be enough. You mentioned DRAM with MIG， VDMA IP..., any example I can refer to so that a data file (image) can be stored into DRAM and processed using FPGA?
Thanks and Regards,
01-30-2019 08:28 PM
Would you refer the following TRD, if you can use MP SoC ?
You can refer this TRD, expecially M2M Pipluines and Output Piplines.
MP SoC already has a DRAM controller in PS side. So, you don't need to implement DRAM controller by MIG IP.
If you use UltraScale+ FPGA, you need to import this TRD to UltraScale+ and change some IP (ex. Zynq and so on) to suitable IP. (ex. Zynq->Microblaze, DRAM controller in PS side->MIG, DP Tx in PS side->DP Tx in FPGA fabric)
01-30-2019 10:52 PM
I have ordered ZCU102 and the TRD is very valuable information.
It'll be quite a learning curve for me, both on the linux and PS side. From the brief reading of TRD user guide, it supports both TPG (PL side) and TPG(SW). That'll fix my need perfectly.
I'm not clear on your suggestion of importing TRD. The TRD is already based on ZCU102, why do I need to change the IP? It seems to me the change involves moving from PS to PL side?
Thanks and Regards,
01-31-2019 03:07 AM
> 'm not clear on your suggestion of importing TRD. The TRD is already based on ZCU102, why do I need to change the IP? It seems to me the change involves moving from PS to PL side?
Because of you already mentioned that you have KCU105 before, I suggest that you need to import TRD from ZCU102.
Of cause, if you use ZCU102 or other MP SoC device, it is easy to refer TRD.
I strongly suggest using ZCU103 or other MP SoC device.
01-31-2019 04:17 AM - edited 01-31-2019 04:23 AM
01-31-2019 11:45 AM