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thenumberdevil
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Registered: ‎04-21-2020

Xilinix-frmbuf framebuffer probe failing

Hi All,

            I am attaching the log while startup and could see the failures in the framebuffer.

[ 0.736889] xilinx-vdma 43000000.dma: Xilinx AXI VDMA Engine Driver Probed!!
[ 0.744400] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 0.752409] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 1.904679] xilinx-vpss-csc 43c30000.v_proc_ss: VPSS CSC 8-bit Color Depth Probe Successful
[ 3.425331] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.433704] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.482486] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.490849] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.499224] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.507631] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.523227] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.536883] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.612929] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 3.621266] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 4.609012] xilinx-frmbuf 43c00000.v_frmbuf_wr: Probe deferred due to GPIO reset defer
[ 4.617965] xilinx-frmbuf 43c40000.v_frmbuf_wr: Probe deferred due to GPIO reset defer

 

Will be helpful if I get some pointers?.

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badegoke_f1
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Registered: ‎06-18-2019

Hi,
I have had similar issue in the past.Try checking your device tree overlay file . System-user.dtsi. Make sure you add gpio reset from your block design in the system-user.dtsi . Something of the lines:

 

	v_frmbuf_wr@b0000000 {
		xlnx,dma-align = <0x20>;
		xlnx,max-width = <0xf00>;
		xlnx,video-width = <0xa>;
		reset-gpios = <&gpio_resets 0x1 0x0 0x1>;
		
	};

 

 

Cheers
Bade

thenumberdevil
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Thank you I will check the same and report back.

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thenumberdevil
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@florentw 

AS per your guidance I have got the drivers of the VPSS up and running.

[ 0.751171] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.758727] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 0.767543] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.775048] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 1.929982] xilinx-vpss-csc 43c30000.v_proc_ss: VPSS CSC 8-bit Color Depth Probe Successful
[ 1.938710] xilinx-vpss-scaler 43d00000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 1.949369] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Hori Taps 6
[ 1.955543] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Vert Taps 6
[ 1.961735] xilinx-vpss-scaler 43d00000.v_proc_ss: VPSS Scaler Probe Successful
[ 1.969208] xilinx-vpss-scaler 43cc0000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 1.979850] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Hori Taps 6
[ 1.986027] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Vert Taps 6
[ 1.992234] xilinx-vpss-scaler 43cc0000.v_proc_ss: VPSS Scaler Probe Successful

But still sub-devices are not visible in the dev.

From the device tree we have  still the axis_switch and test pattern generator Which is not initialized. I presume that it should not be a problem.

Let me know what I am missing ?.

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florentw
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Hi @thenumberdevil 

You probably need to have the full pipeline up before you can see the subdevices. So you need to have the TPG up as well


Florent
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thenumberdevil
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Hi @florentw ,

                            When I initailize the TPG driver I am getting the problem with GPIO initialization. Our tpg IP reset is connected to VCC.

If so how should I specify the reset-gpios in the device tree. Or should we connect the IP to a local reset gpio instead of VCC.

 

thenumberdevil_0-1597149368695.png

 

 

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florentw
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Hi @thenumberdevil 

Yes the TPG IP needs to be connected to an AXI GPIO as well...

If you have follow up question, please create a new topic as this is not related anymore to the video frame buffer (which is not probed successfully)


Florent
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thenumberdevil
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Hi @florentw,
Understood. Will do the same
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thenumberdevil
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Hi @florentw ,

                        I got all the IP core in the system up and running.But not able to see the  subdev node(/dev/v4l-subdev*). I am attaching the log which I received for the same.

[ 0.757272] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.764829] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 0.773629] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.781135] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 1.935649] xilinx-tpg 43c60000.v_tpg: device found, version 0.000
[ 1.942358] xilinx-vpss-csc 43c30000.v_proc_ss: VPSS CSC 8-bit Color Depth Probe Successful
[ 1.951154] xilinx-vpss-scaler 43d00000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 1.961820] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Hori Taps 6
[ 1.968025] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Vert Taps 6
[ 1.974221] xilinx-vpss-scaler 43d00000.v_proc_ss: VPSS Scaler Probe Successful
[ 1.981667] xilinx-vpss-scaler 43cc0000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 1.992322] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Hori Taps 6
[ 1.998524] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Vert Taps 6
[ 2.004716] xilinx-vpss-scaler 43cc0000.v_proc_ss: VPSS Scaler Probe Successful

 

Thank you once again  for prompt support.

 

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thenumberdevil
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Hi @florentw ,

I got  the vdma ip core driver as well initialized.

[ 0.768088] xilinx-vdma 43000000.dma: Xilinx AXI VDMA Engine Driver Probed!!
[ 0.775887] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.783442] xilinx-frmbuf 43c00000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 0.792183] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI frmbuf DMA_DEV_TO_MEM
[ 0.799758] xilinx-frmbuf 43c40000.v_frmbuf_wr: Xilinx AXI FrameBuffer Engine Driver Probed!!
[ 1.955180] xilinx-tpg 43c60000.v_tpg: device found, version 0.000
[ 1.961806] xilinx-vpss-csc 43c30000.v_proc_ss: VPSS CSC 8-bit Color Depth Probe Successful
[ 1.970529] xilinx-vpss-scaler 43d00000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 1.981192] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Hori Taps 6
[ 1.987395] xilinx-vpss-scaler 43d00000.v_proc_ss: Num Vert Taps 6
[ 1.993593] xilinx-vpss-scaler 43d00000.v_proc_ss: VPSS Scaler Probe Successful
[ 2.001039] xilinx-vpss-scaler 43cc0000.v_proc_ss: xlnx,v-vpss-scaler-1.0 - compatible string is getting deprecated!
[ 2.011698] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Hori Taps 6
[ 2.017904] xilinx-vpss-scaler 43cc0000.v_proc_ss: Num Vert Taps 6
[ 2.024096] xilinx-vpss-scaler 43cc0000.v_proc_ss: VPSS Scaler Probe Successful

 

 

 

 

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florentw
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HI @thenumberdevil 

Once again you need to check the full pipeline. You might want to refer to the wiki page for the linux driver of the video frame buffer write:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842236/Video+Framebuffer+Write

If you had follwed the testing procedure mentioned you would have started by verifying the status of your media pipleline, run the tool known as "media-ctl":

media-ctl -p

Florent
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thenumberdevil
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Hi @florentw ,

                         I will check that. But in general, When I enable a driver for a IPCORE and if it is successful, Then it should list out in subdevices for the same.Am I missing any other important point to consider in the pipeline. 

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thenumberdevil
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Hi @florentw ,

                        Thank you for the guidance. When I remove video  the following things

# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
# CONFIG_V4L_MEM2MEM_DRIVERS is not set
# CONFIG_V4L_TEST_DRIVERS is not set

I am not able to see any /dev/video enty in the /dev folders.

1.Is this pipeline categorized as CONFIG_V4L_MEM2MEM_DRIVERS. If so , should I follow this  idea

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/80707675/Mem+2+Mem+VPSS-CSC+VPSS-SC+device

 

 

 

 

 

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florentw
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HI @thenumberdevil 

Good to see that you are making progress.

The type of pipeline will depend on the logic you have. If your video stream is coming from memory and going to memory then you would use the mem2mem framework.

However, I believe that in your case the stream in not coming from memory but from a capture device (this is coming from the TPG which can be considered as a capture device and I guess you will replace it with a connectivity IP?). So in this case, you should not use the mem2mem framework but the v4l2 framework


Florent
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thenumberdevil
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Hi @florentw ,

Before initializing all the ip core drivers I should initialize this driver.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841767/Xilinx+V4L2+driver

This driver  provide the main /dev/video interface.

 

 

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florentw
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Hi @thenumberdevil 

You need to make sure the settings are correctly set but that's all. The other V4L2 (including the video frame buffer) are part of the V4L2 driver framework.

Refer to the VCU TRD or Zynq MPSoC TRD which are using the V4l2 drivers


Florent
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thenumberdevil
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Hi @florentw ,

                       I refered to the document you have pointed out. I think I have a better overall system understanding.

As a first step,In my case With TPG driver, framebuffer write driver and VIPP driver I should have see the v4l device and TPG as a subdevice.

How to enable the VIPP driver. As I see that as the main driver which registers all the subdevices.

By greping i could see that VIPP driver is present in the kernel.If so how to make sure  that xvipp

driver is intialized properly and registering the pipeline.

Thank you for the support.

 

 

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florentw
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HI @thenumberdevil 

I guess the way to make sure the xvipp is working properly is adding debug message in it if you do not see the subdevices.

But again as mentioned, you need to make sure every device is probed properly first. So make sure you check your log completely and there is no error in the devices probe.

Again make sure you look at the device tree from the VCU TRD example files so you can make sure nothing is missing in yours.

Regards


Florent
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thenumberdevil
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Hi @florentw 

I have been going through this link

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841767/Xilinx+V4L2+driver  and I see the dts is defined for the same. Do I need to define the same. What I am missing here. As xvipp serve as a base driver for binding all the subdevices together.

In your previous post you mentioned to check the device treee in the VCU TRD, Could you please provide link to the same?

 

Thank you.

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thenumberdevil
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Hi @florentw ,

                         I am external building the xilinx-vipp driver. I have two issues

The driver is not recognizing the dma modules symbols. So I commented them  to make the driver load.

The device get registered but could not see the subdevices

[ 1383.106681] xlnx_vipp amba_pl:axi_video_cap: parsing node /amba_pl/axi_video_cap
[ 1383.114082] xlnx_vipp amba_pl:axi_video_cap: handling endpoint /amba_pl/axi_video_cap/ports/port@0/endpoint
[ 1383.123981] xlnx_vipp amba_pl:axi_video_cap: parsing node /amba_pl/v_tpg@43c60000
[ 1383.131491] xlnx_vipp amba_pl:axi_video_cap: handling endpoint /amba_pl/v_tpg@43c60000/ports/port@0/endpoint
[ 1383.141363] xlnx_vipp amba_pl:axi_video_cap: Entity type for entity 43c60000.v_tpg was not initialized!
[ 1383.150791] xlnx_vipp amba_pl:axi_video_cap: subdev 43c60000.v_tpg bound
[ 1383.157518] xlnx_vipp amba_pl:axi_video_cap: notify complete, all subdevs registered
[ 1383.165254] xlnx_vipp amba_pl:axi_video_cap: creating links for entity 43c60000.v_tpg
[ 1383.173181] xlnx_vipp amba_pl:axi_video_cap: processing endpoint /amba_pl/v_tpg@43c60000/ports/port@0/endpoint
[ 1383.183248] xlnx_vipp amba_pl:axi_video_cap: skipping DMA port /amba_pl/v_tpg@43c60000:0
[ 1383.191373] xlnx_vipp amba_pl:axi_video_cap: creating links for DMA engines
[ 1383.198397] xlnx_vipp amba_pl:axi_video_cap: processing endpoint /amba_pl/axi_video_cap/ports/port@0/endpoint
[ 1383.208349] xlnx_vipp amba_pl:axi_video_cap: no DMA engine found for port 0,

Could you please let me know what I am missing?

 

Questions

1. What I am missing here.

 

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florentw
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Hi @thenumberdevil 

Refer to the device tree bindings for the drivers for the required parameters.

This is the link to the VCU TRD:

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/460948332/Zynq+UltraScale+MPSoC+VCU+TRD+2020.1


Florent
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thenumberdevil
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Hi @florentw ,

                       Thank you for the guidance and relentless support.

As a fist step I have connected the VIPP bridge driver with  the TPG. To make sure the pipeline is getting initialized properly. 

I had a problem because the compatible keyword in the device tree configuration was mismatching with  the one in the vipp driver(bridge driver). After correcting it I could see the /dev/video0 and the TPG(Test pattern generator) as a sub device under /dev.

Further I will be adding all the sub devices(CSC, scalers ... ) and will report the same in this thread.

thenumberdevil
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Hi @florentw ,

                      I have some questions related to the TPG IP block.

Precondition

                    On booting baremetal application is intializing the TPG IP BLOCK.

What is happening

                   While linux booting the TPG driver is probed. Which causes the system to freeze.

I am using the TPG driver from the xilinx. Hoped it should work out of box? .Any suggestions?.

 

 

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florentw
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HI @thenumberdevil 

I do not know. Yes the TPG driver should work and is working in examples as the VCU TRD

I would suggest you create a new topic on the Embedded Linux board (make sure you share the log) to get help from linux expert (which I am not really)


Florent
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thenumberdevil
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@florentw 

                      Will do as you suggested. You are the only person who respond in record time :-).