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Adventurer
Adventurer
858 Views
Registered: ‎03-08-2018

Xilinx Gamma LUT IP

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Hi,

     We are trying to implement an image processing pipeline involving Gamma LUT. Our pipeline consists of these IPs.

1.Video stream to AXI

2.Demosaic

3.Gamma LUT

4.VPSS

Without Gamma LUT we are able to obtain proper output.But when I include the Gamma LUT, some kind of noise comes into picture. To debug this I used gamma value 1 and loaded the table with values 0 to 255.

I am using XV_gamma_lut_Write_HwReg_gamma_lut_0_Bytes this function to load the values.

My SDK is

XV_gamma_lut_DisableAutoRestart(gamma_lut_ptr);
                    XV_gamma_lut_Set_HwReg_width(gamma_lut_ptr, 400);
                    XV_gamma_lut_Set_HwReg_height(gamma_lut_ptr, 400);
                    XV_gamma_lut_Set_HwReg_video_format(gamma_lut_ptr, 0);
                    XV_gamma_lut_Write_HwReg_gamma_lut_0_Bytes(gamma_lut_ptr,0,(char *)gamma_lut_values,256);
                    XV_gamma_lut_Write_HwReg_gamma_lut_1_Bytes(gamma_lut_ptr,0,(char *)gamma_lut_values,256);
                    XV_gamma_lut_Write_HwReg_gamma_lut_2_Bytes(gamma_lut_ptr,0,(char *)gamma_lut_values,256);
                    XV_gamma_lut_EnableAutoRestart(gamma_lut_ptr);
                    XV_gamma_lut_Start(gamma_lut_ptr);

 

u8 gamma_lut_values[256] = {0,1,2,3,4,5,6,7,8,9,10,
        11,12,13,14,15,16,17,18,19,20,
        21,22,23,24,25,26,27,28,29,30,
        31,32,33,34,35,36,37,38,39,40,
        41,42,43,44,45,46,47,48,49,50,
        51,52,53,54,55,56,57,58,59,60,
        61,62,63,64,65,66,67,68,69,70,
        71,72,73,74,75,76,77,78,79,80,
        81,82,83,84,85,86,87,88,89,90,
        91,92,93,94,95,96,97,98,99,100,
        101,102,103,104,105,106,107,108,109,110,
        111,112,113,114,115,116,117,118,119,120,
        121,122,123,124,125,126,127,128,129,130,
        131,132,133,134,135,136,137,138,139,140,
        141,142,143,144,145,146,147,148,149,150,
        151,152,153,154,155,156,157,158,159,160,
        161,162,163,164,165,166,167,168,169,170,
        171,172,173,174,175,176,177,178,179,180,
        181,182,183,184,185,186,187,188,189,190,
        191,192,193,194,195,196,197,198,199,200,
        201,202,203,204,205,206,207,208,209,210,
        211,212,213,214,215,216,217,218,219,220,
        221,222,223,224,225,226,227,228,229,230,
        231,232,233,234,235,236,237,238,239,240,
        241,242,243,244,245,246,247,248,249,250,
        251,252,253,254,255};

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Moderator
Moderator
787 Views
Registered: ‎11-09-2015

Hi @kannan,

I am not sure if it is really wrong. It seems that the white part are becoming black and the black part are becoming white. From what I understand you give the value 255 to all the component with the value 0 and the value 0 to all the components with the value 255.

I would say that if you fill the value in the other way (255 to 0), you might get the same image.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

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Highlighted
Moderator
Moderator
788 Views
Registered: ‎11-09-2015

Hi @kannan,

I am not sure if it is really wrong. It seems that the white part are becoming black and the black part are becoming white. From what I understand you give the value 255 to all the component with the value 0 and the value 0 to all the components with the value 255.

I would say that if you fill the value in the other way (255 to 0), you might get the same image.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Adventurer
Adventurer
760 Views
Registered: ‎03-08-2018

Hi,         

I solved the problem by using XAPP 794 reference design. Now it is working fine.

Thanks

Kannan