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Registered: ‎06-10-2019

Xilinx HDMI RX driver support on multi-planner

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Hi,

I am using Zynq Ultrascale+ (ZCU106). I would like to use HDMI RX/ Frame buffer write driver with Multi-planner API. I got it working with single-planner with Continuous frame buffer. I would like to use  Multi-planner API for fragmented frame buffer.

I tried with 2, 4 , 8 planes but doesn't work. I would like to know if it is supported. 

it only works with single planner format.

HDMI RX ---> FrameBuffer write ----> DDR.

Has anyone has any idea if it works? Does Xilinx HDMi Rx driver support V4L2 Multi-planner? I have no idea what type of DMA used on FrameBuffer WR IP like S-G DMA?

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@systemsdeveloper 

The main question is not related to HDMI driver, it's Framebuffer.

It has been mentioned in Framebuffer write wikipage, it can support 2 planes : One for Luma, and the other for Chroma

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842236/Video+Framebuffer+Write

I don't know how you implement 4 planes, or 8 planes. 

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Registered: ‎06-10-2019

I am referring to this type of application, Multi-Planner API example provided....

https://people.freedesktop.org/~narmstrong/meson_drm_doc/media/uapi/v4l/mmap.html#example-mapping-buffers-in-the-multi-planar-api

any suggestion ?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

@systemsdeveloper 

The main question is not related to HDMI driver, it's Framebuffer.

It has been mentioned in Framebuffer write wikipage, it can support 2 planes : One for Luma, and the other for Chroma

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842236/Video+Framebuffer+Write

I don't know how you implement 4 planes, or 8 planes. 

View solution in original post

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Registered: ‎06-10-2019

@xud 

Thanks for reply. Yes, I found similar information on Framebuffer IP and from provided frame buffer driver code. its support only 2 planes. 

I didn't success with more than 2 planes. My original questions was V4L2 layer support multiple planes if HDMI/Framebuffer driver support. This is only possible if SG DMA is used in Framebuffer IP. This is very handy feature if IP supported. This will avoid extra SW copy on frame buffer when you want to play with external device for CNN/ML/compression on capture frame if your external device doesn't work with contiguous memory manner or running on different memory area. 

Anyway, Thanks for your reply.

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