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bjnew
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Registered: ‎01-15-2021

ZCU104 board: No HDMI TX data pin definition in auto-generated HDMI example contraints file

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Hi,

I am now trying to run HDMI TX example on ZCU104 board.

I follow the guide of pg235-v-hdmi-tx-ss.pdf to generated the example code in Vivado 2018.2, and the generated contraints file v_hdmi_tx_ss_0_ex/imports/hdmi_example_zcu104.xdc is as following.

Could anyone tell me why there is not  HDMI TX data pins' definition in this constraints file?  

 

#####
## Constraints for ZCU104 FMC HDMI 2.0
## Version 1.0
#####


#####
## Pins
#####

# TBD
set_property PACKAGE_PIN M11 [get_ports reset]
set_property IOSTANDARD LVCMOS33 [get_ports reset]

# HDMI TX
set_property PACKAGE_PIN T8 [get_ports TX_REFCLK_P_IN]

# rev B
set_property PACKAGE_PIN G21 [get_ports {HDMI_TX_CLK_P_OUT}]
set_property IOSTANDARD LVDS [get_ports {HDMI_TX_CLK_P_OUT}]

# TBD
# set_property PACKAGE_PIN G8 [get_ports tmds_clk_out]
# set_property IOSTANDARD LVCMOS33 [get_ports tmds_clk_out]

set_property PACKAGE_PIN E3 [get_ports TX_HPD_IN]
set_property IOSTANDARD LVCMOS33 [get_ports TX_HPD_IN]

set_property PACKAGE_PIN B1 [get_ports TX_DDC_OUT_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports TX_DDC_OUT_scl_io]

set_property PACKAGE_PIN C1 [get_ports TX_DDC_OUT_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports TX_DDC_OUT_sda_io]


# I2C
set_property IOSTANDARD LVCMOS33 [get_ports fmch_iic_scl_io]
set_property PACKAGE_PIN D1 [get_ports fmch_iic_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports fmch_iic_sda_io]
set_property PACKAGE_PIN E1 [get_ports fmch_iic_sda_io]

# Misc
#GPIO_LED_0_LS
set_property PACKAGE_PIN D5 [get_ports LED0]
set_property IOSTANDARD LVCMOS33 [get_ports {LED0}]

set_property PACKAGE_PIN M12 [get_ports IDT_8T49N241_RST_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports IDT_8T49N241_RST_OUT]

set_property PACKAGE_PIN N11 [get_ports IDT_8T49N241_LOL_IN]
set_property IOSTANDARD LVCMOS33 [get_ports IDT_8T49N241_LOL_IN]

set_property PACKAGE_PIN A2 [get_ports TX_EN_OUT]
set_property IOSTANDARD LVCMOS33 [get_ports TX_EN_OUT]

# TBD - not needed as it is duplicated of TX_EN_OUT
# set_property PACKAGE_PIN C2 [get_ports {RX_LS_OE[0]}]
# set_property IOSTANDARD LVCMOS33 [get_ports {RX_LS_OE[0]}]

#####
## End
#####

 

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xud
Xilinx Employee
Xilinx Employee
144 Views
Registered: ‎08-02-2007

@bjnew 

If you don't have more questions related to this, can you close this thread by marking  accept solution please?

View solution in original post

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xud
Xilinx Employee
Xilinx Employee
164 Views
Registered: ‎08-02-2007

@bjnew 

Once GT Channel Location is selected in Video PHY GUI, the txp/n are fixed. The GT Channel LOC constraint is generated with Video PHY.

The screenshot below shows how to find scoped constraint file, which contains GT channel LOC constraint. 

xud_0-1611140829717.png

 

bjnew
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Registered: ‎01-15-2021

Get it ,thanks a lot!

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xud
Xilinx Employee
Xilinx Employee
145 Views
Registered: ‎08-02-2007

@bjnew 

If you don't have more questions related to this, can you close this thread by marking  accept solution please?

View solution in original post

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