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Assaf_Almog
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Registered: ‎03-16-2021

ZCU106 VCU TRD (2020.2) - vivado project build errors

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Hi,

I'm trying to build the zcu106_pcie vivado project, as described in 

Zynq UltraScale+ MPSoC VCU TRD 2020.2 - Run and Build Flow - Xilinx Wiki - Confluence (atlassian.net)

I'm using Vivado 2020.1, running on a Linux machine.

During the project build (from project.tcl) I'm getting error messages regarding the GTY_Quad_128 and for the PCIE4C_X0Y1 components in the block design - "Value xxx is out of range for parameter yyy for BD Cell.

It seems to me that the design does not match the device on the ZCU106 board.

Any Ideas anyone?

Thanks,

Assaf

 

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florentw
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Registered: ‎11-09-2015

HI @Assaf_Almog 

I just tried with 2020.2 on RHEL 7.4 and did not face any error while sourcing the TCL file. I can see in the PCIE IP that the location has been correctly set to X0Y1

florentw_0-1617804858246.png

 

So I would recommend using a supported OS and maybe 2020.2


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

Hi @Assaf_Almog 

Just to clarify: you are trying to build the VCU TRD 2020.2 in 2020.1? Why?

The VCU TRD has a 2020.1 release: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/504398119/Zynq+UltraScale+MPSoC+VCU+TRD+2020.1+-+Run+and+Build+Flow 

would you try it? Or move to 2020.2?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Assaf_Almog
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Registered: ‎03-16-2021

Sorry, 

I'm using Vivado 2020.2.1.

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florentw
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Registered: ‎11-09-2015

Hi @Assaf_Almog 

Ok let me try to build it.

What exact OS + version are you using? Did you make sure this is in the list of the supported OS?

PS: Is there any specific reason why you are using 2020.2.1 and not 2020.2 (are you using a specific device)? If not the recommendation is to keep using 2020.2 as per the note in the 2020.2.1 downloading section:

Download Vivado® Design Suite 2020.2.1 now, with support for

  • Additional CIV/ULT Devices:- XCKU095_CIV, XCVU190_CIV, XCVU47P_CIV
  • New package additions to XCZU2CG/EG and XCZU3CG/EG devices


For customers using these devices, Xilinx recommends installing Vivado 2020.2.1
For other devices, please continue to use Vivado 2020.2.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Assaf_Almog
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I'm running on a CentOS 6.5 machine.

No specific reason for using 2020.2.1. I can switch to 2020.2 and try to build again..

Thanks,

Assaf

 

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florentw
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Registered: ‎11-09-2015

HI @Assaf_Almog 

I can try with 2020.2 first and let you know.

Also CentOS 6.5 is not is the list of the supported OS for 2020.2:

florentw_0-1617804363016.png

 

I do not have a handy access to a CentOS machine so I will try with a RHEL 7.4. This will give us an idea if it is a design issue or an issue with your system


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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florentw
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Registered: ‎11-09-2015

HI @Assaf_Almog 

I just tried with 2020.2 on RHEL 7.4 and did not face any error while sourcing the TCL file. I can see in the PCIE IP that the location has been correctly set to X0Y1

florentw_0-1617804858246.png

 

So I would recommend using a supported OS and maybe 2020.2


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post