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tim_severance
Scholar
Scholar
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Registered: ‎03-03-2017

Zynq US+ DP 1.4 TX design low power thermal

I am working on a Zynq US+ (4CG) design for DP 1.4 TX only which will be used in a production test environment where test time is very important.   We are having concerns about how hot the FPGA is going to get in our design and I am wondering if there is an idle state I can put the design into when it is not being used and if so how quickly it can be woken up.   Also, if there is a low power state that you recommend, is there a way to determine how much cooler the FPGA would be in that state?

Does somebody know of a low power mode state for the DP 1.4 TX design?

Thanks.

Tim

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watari
Teacher
Teacher
114 Views
Registered: ‎06-16-2013

Hi @tim_severance 

 

How about disabling Main Link to go to a low power mode ?

 

https://www.xilinx.com/support/documentation/ip_documentation/v_dp_txss1/v3_0/pg299-v-dp-txss1.pdf#page=41

 

Best regards,

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