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Gloria_gao
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Registered: ‎11-15-2020

csi2-rx-ip example for SP701

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I feel confused about the data width transformation between csi2-rx-ip and demoasic ip.  In this exampel, the data type selected in csi-rx-ip is RAW10, as the figure below:

2.png

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

so the data output width is 24.

For demosaic ip, the data input width is equal to data type*samples_per_clock. So I think the data input width should be 32. But the width in demosaic is 16.

2.png

Why the data width in this example is 16?

How to make width 24 of RAW 10 to width 16 of RAW 10. It seems to be that some pixels must be deleted. 

 

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Gloria_gao
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Registered: ‎11-15-2020

Hi, @florentw 

For this example, the data type of csi2-ip is RAW10,so the data width of the demosaic IP should be 10 bit. Is it right?

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florentw
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Registered: ‎11-09-2015

HI @Gloria_gao 

The answer is in the following topic (you might want to give kudos to the reply from @karnanl 

https://forums.xilinx.com/t5/Video-and-Audio/MIPI-CSI2-RX-Subsystem-Example-Bit-Width/td-p/1190323 

First note that RAW10 with 2 pixels per clock requires only 20-bits. The interface needs to follow the AXI4 spec so tdata needs to be a multiple of 8, thus 24-bits is the closest

The design was initially made for 8-bits data. So the 2 LSB from the RAW10 will be ignored (it is like receiving RAW8). So on the output of the demosaic IP, you will have RGB 8-bits.

Thus no pixel is ignored, they have just a lowest precision.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Gloria_gao
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Registered: ‎11-15-2020

Hi, @florentw 

For this example, the data type of csi2-ip is RAW10,so the data width of the demosaic IP should be 10 bit. Is it right?

View solution in original post

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florentw
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Registered: ‎11-09-2015

HI @Gloria_gao 

The type from yhr MIPI CSI2 IP is indeed RAW10. But the xslices IP are used to take the 8-bit MSB from this to feed the demosaic IP as if it was RAW8. This is how the design was made

You can change the demosaic IP to 10 bit but you would need to make further changes to the design (first remove the xslice IPs and make sure the downstream IPs are also configured for 10-bits)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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