07-20-2018 12:19 AM
I have to insert my video processing system in my vivado project with VDMA and Axis-Stream to Video Out, basically , from what I understand now , I have to have a block with a s_axis_video and m_axis_video, I have followed UG934, and I based myself in a project with a DMA and a custom FIFO AXis stream , where I add the block to generate EOL and SOF , and tried to follow the template that the UG934 shows.
entity axis_fifovid_v1_0 is
-- Users to add parameters here
ADDR_WIDTH : integer := 12;
C_AXIS_TDATA_WIDTH : integer := 24;
-- User parameters ends
-- Do not modify the parameters beyond this line
C_S0_DATA_WIDTH : integer := 24;
C_S0_VIDEO_FORMAT : integer := 2;
C_S0_AXIS_TDATA_WIDTH : integer := 24;
C_S0_MAX_SAMPLES_PER_CLOCK : integer := 1;
C_M0_DATA_WIDTH : integer := 24;
C_M0_VIDEO_FORMAT : integer := 2;
C_M0_AXIS_TDATA_WIDTH : integer := 24;
C_M0_MAX_SAMPLES_PER_CLOCK : integer := 1
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S00_AXIS
s_axis_video0_aclk : in std_logic;
s_axis_video0_aresetn : in std_logic;
s_axis_video0_tready : out std_logic;
s_axis_video0_tdata : in std_logic_vector(C_S0_DATA_WIDTH-1 downto 0);
s_axis_video0_tlast : in std_logic;
s_axis_video0_tuser : in std_logic;
s_axis_video0_tvalid : in std_logic;
-- Ports of Axi Master Bus Interface M00_AXIS
m_axis_video0_aclk : in std_logic;
m_axis_video0_aresetn : in std_logic;
m_axis_video0_tvalid : out std_logic;
m_axis_video0_tdata : out std_logic_vector(C_M0_DATA_WIDTH-1 downto 0);
m_axis_video0_tlast : out std_logic;
m_axis_video0_tuser : out std_logic;
m_axis_video0_tready : in std_logic
so UG934 says : "
"but I haven't found this HDL source yet ... so someone has any tip about such systems (custom IP)
or examples of S_AXIS_VIDEO M_AXIS_VIDEO interfaces ... please.
07-23-2018 01:37 AM
The Video to AXI4-Stream and AXI4-Stream to Video cores are delivered as HDL source code and provided as examples to expedite custom interface development.
--> This means that the source for the Video In to AXI4-Stream IP or the AXI4-Stream to Video Out are unencrypted HDL in vivado. You will find it below the IP:
However to be honest I am not sure if it is the best starting point for your interfaces.
You might want to consider Vivado HLS for an easiest way to create custom AXI4S video IPs.
If you want to do it in HDL, the AXI4S interface is not really complicated even more if you already have an input. You just need to take care of the handshaking and propagate the EOF and SOF for your input to output.
Hope that helps,
07-23-2018 08:28 AM
07-25-2018 12:48 AM
I used the AXI4S FIFO in a video design and it was working fine. I was able to get data in and out.
You might want to check if the master is correctly sending data and if the slave is ready to receive it
07-25-2018 08:56 AM
right now I created a module where I just connect the handshaking lines : tvalid and t ready , and propagate tlast and tuser , I will post the solution I took once I have more confidence that is working properly, I guess the documentation UG934 mentions this approach.
07-30-2018 01:36 PM
I kinda have some result when I connect READY and VALID , plus EOL and SOF , but because I have buffers in my code, a FIFO, the output shows the image broken like you see in the picture, with a dead region in the image. It would be easier if Xilinx provided more HDL code for this interface.
07-30-2018 11:07 PM
The interface is not really difficult to do if you already have an input. And it is not completely possible to do a template as it will depends on how your block will or work (continuous flow or not)
And again, for an easiest solution you can still use vivado hls
08-14-2018 06:10 AM
Do you have any updates on this? Do you still require any assistance?
Thanks and Regards,
08-27-2018 07:43 AM
still struggling :(
have been trying to follow ug934 ....
my IP is basically a bridge with receiving data via slave stream and transmitting data with master stream , for the real time video .. another option is to use full AXI4 from the VDMA to PS , but up to now I have not found examples of HLS implementing full AXI4 slave and master (kinda a custom AXI Interconnect with my IP inside).
08-28-2018 12:17 AM