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728 Views
Registered: ‎01-20-2020

issue driving MIPI D-PHY RX mode

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Hello

I need to use MIPI D-PHY ip core in RX mode with 4 lanes. I ran the ip example design, although the simulation is running, there is no activity on the clocks and data. anyone can help?

I am using MIPI D-PHY v4.1 in vivado 2019.2.1

Best
Amin

1 Solution

Accepted Solutions
karnanl
Xilinx Employee
Xilinx Employee
699 Views
Registered: ‎03-30-2016

Hello amin@zadarlabs.com 

Unfortunately, MIPI IP simulation takes a lot of time.
Mainly because MIPI D-PHY TX has big INIT_VAL value as a default setting.

Please see PG202 Table 2-22 for INIT_VAL register explanation.
(for MIPI D-PHY TX : 1 ms, for MIPI D-PHY RX : 100 us )

During the initialization process MIPI TX needs to set output lanes into LP-11 state, to make the initialization process successful. You can adjust your INIT_VAL setting to meet your system requirements. (Please refer to MIPI D-PHY specification for more detailed information )

So, if you want to run a shorter/faster simulation,

1. You can use a lower INIT_VAL register setting.  ( for example 150us )
    -- Modify the register setting. ( or you can also modify C_INIT setting on your XCI file )
2. You may also try to run the simulation using another simulator (if you have access to a simulator other than Vivado Simulator).  I found NCSIM runs a lot faster.

Best regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

3 Replies
karnanl
Xilinx Employee
Xilinx Employee
703 Views
Registered: ‎03-30-2016

Hello amin@zadarlabs.com 

Please run the simulation more than 1.2ms

Regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------
karnanl
Xilinx Employee
Xilinx Employee
700 Views
Registered: ‎03-30-2016

Hello amin@zadarlabs.com 

Unfortunately, MIPI IP simulation takes a lot of time.
Mainly because MIPI D-PHY TX has big INIT_VAL value as a default setting.

Please see PG202 Table 2-22 for INIT_VAL register explanation.
(for MIPI D-PHY TX : 1 ms, for MIPI D-PHY RX : 100 us )

During the initialization process MIPI TX needs to set output lanes into LP-11 state, to make the initialization process successful. You can adjust your INIT_VAL setting to meet your system requirements. (Please refer to MIPI D-PHY specification for more detailed information )

So, if you want to run a shorter/faster simulation,

1. You can use a lower INIT_VAL register setting.  ( for example 150us )
    -- Modify the register setting. ( or you can also modify C_INIT setting on your XCI file )
2. You may also try to run the simulation using another simulator (if you have access to a simulator other than Vivado Simulator).  I found NCSIM runs a lot faster.

Best regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

View solution in original post

688 Views
Registered: ‎01-20-2020
Many thanks Leo. worked.