mipi dsi tx core output clock is incorrect

[aawce]

Hi,

I'm using the  MIPI dsi tx core, and setting it to 350MHz line rate.  However after implementing the design, the actual output clocks are divided by 4, that is I only see ~87Mhz on oscilloscope, and Vivado clock report says the same. 

Here's the DSI-TX configuration (note 350Mbs Line Rate):

And here's Vivado clock report:

When probing into the implemented netlist I see the bitslice is implemented a divide by 4.  Why is this and how do we fix it so we get the rate we are specifying?

Thanks,

Chris

[karnanl]

Hello Chris @aawce

@chrisar

1. MIPI is using DATA_WIDTH=8, so DIV_MODE=4 is an expected setting. (no issue on this)

2. 87.5 MHz is also an expected PLL clock output.

    You should be see clock connectivity as shown at diagram below.

3. But I think I do see some unexpected byteclkhs  configuration for

    dphy_tx_fab_top & dsi_tx_ctrl_0. Let me check with MIPI team and give you a feedback on this.

Thanks & regards

Leo

[karnanl]

Hello @aawce

4. You should see 350/2=125 MHz clock serial line. ( Note that MIPI clock is a DDR )

    I confirmed that using 350Mbps setting, the txbyeclkhs is 87.5/2MHz, which is not an expected value.

I cannot give you a feedback today, since today is a National holiday for our MIPI team.

Please wait until tomorrow.

Thanks & regards

Leo

[karnanl · Accepted solution]

Hello @aawce

Per our conversation via email, it seems that you have solved your problem. Thank you very much for your effort.

1. This is not a bug of MIPI DSI TX IP.
   For line-rate setting less than 600Mbps, MIPI D-PHY is adopting oversampling mode to run the MIPI D-PHY core with different mode depending on line-rate.
   With 350Mbps setting, all clock from PLL output has an expected frequency.
   ( Shown in your previous post clkoutphy_out_DIV=87.5MHz is also expected)
    

2. MIPI DSI TX timing register setting will not affect MIPI D-PHY serial clock output frequency.
   So, MIPI D-PHY clock is always 175MHz ( 350MHz/2), if we set line-rate as 350Mbps.
   
3. Issue is solved after MIPI DSI TX timing register modification, so HFP/HBP value can meet the Display spec requirement.

Thanks & regards
Leo

[aawce]

Hi Leo,

Yes, thank you.  I'm not sure how we were seeing the slower 87MHz clock on the output, but now that we have corrected the Horizontal and Vertical porch timings for the display we see correct operation (consistent 175MHz on the clock lines for 350Mbs DSI MIPI rate).

To confirm, we got confused by the Vivado clock report saying 87MHz for txbyteclkhs and now that you have provided how the D-PHY implements oversampling, we now confirm correct implementation and Vivado logs for the design.

Thank you your help.

-Chris

[florentw]

HI @aawce,

As this is now clear for you, could you kindly close the topic by marking @karnanl's reply as accepted solution (click on accept as solution below the reply while logged in)?

This might help other members having the same question.

Regards,