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Contributor
Contributor
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Registered: ‎01-27-2019

reduce the axi-lite clock in a hdmi passthrough application

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While working on a very simple hdmi passthrough on a board with microblaze, I could not reduce the axi-lite  clock to below 55MHz. Whenever, I set the clock to below 55MHz, there will have no hdmi output.  But why?

Please advise

 

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Moderator
Moderator
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Registered: ‎10-04-2017

Hi @dr.elichan,

 

The AXI-Lite clock (not stream clock) is responsible for helping characterize the incoming TMDS clock (RX) as well as for assisting with servicing interrupts and configuring the cores.
Does your design have the ability to do TX only? If so, please test to verify that the issue is with the RX side of the passthrough design.

Steps to debug:

  1. Are the cores being initialized? You can check this by using the HDMI API to check status/debug.
    1. If the cores are not being initialized, there is likely an issue with the AIX bus.
      1. Verify AXI transactions are completing.
        1. If there are no completing AXI transitions there is an issue with the AXI bus.
        2. If you are updating clock settings, are you re-exporting your hardware and updating the BSP/Platform?
        3. A stale BSP/Platform can cause many issues.
  2. Is your MB Application stalling at any point?
    1. The HDMI cores rely on interrupt processing form the processor to work correctly.
  3. If the application is running and the cores are being initialized:
    1. Please provide debug/status logs and IP version.
    2. Use example design to replicate the issue. If the example design shows an issue there may be an issue with the core (not likely if using a recent version of the core - very stable at this point)

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post

1 Reply
Moderator
Moderator
200 Views
Registered: ‎10-04-2017

Hi @dr.elichan,

 

The AXI-Lite clock (not stream clock) is responsible for helping characterize the incoming TMDS clock (RX) as well as for assisting with servicing interrupts and configuring the cores.
Does your design have the ability to do TX only? If so, please test to verify that the issue is with the RX side of the passthrough design.

Steps to debug:

  1. Are the cores being initialized? You can check this by using the HDMI API to check status/debug.
    1. If the cores are not being initialized, there is likely an issue with the AIX bus.
      1. Verify AXI transactions are completing.
        1. If there are no completing AXI transitions there is an issue with the AXI bus.
        2. If you are updating clock settings, are you re-exporting your hardware and updating the BSP/Platform?
        3. A stale BSP/Platform can cause many issues.
  2. Is your MB Application stalling at any point?
    1. The HDMI cores rely on interrupt processing form the processor to work correctly.
  3. If the application is running and the cores are being initialized:
    1. Please provide debug/status logs and IP version.
    2. Use example design to replicate the issue. If the example design shows an issue there may be an issue with the core (not likely if using a recent version of the core - very stable at this point)

 

-Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub

View solution in original post