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Adventurer
Adventurer
2,685 Views
Registered: ‎04-08-2009

sysgen CIC variable rate input is a signed fixed point input

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I implemented the CIC compiler 2.0 core in system generator in simulink with the option for a variable rate input.
I set the min rate to be 4 and max rate to be 32 with start up rate of 32.
When I checked the type for the input "rate" of the cic core implementation, it showed that it's a signed fixed point with word length 6, fractional length 0.

 

Is it just me or is that weird for a rate input to be signed?



In simulation I had to input -32 as a rate to get the core to decimate by 32 samples although the core did produce a rdy high every 32 samples in this case

After synthesizing and implementing the design, for any rate requested, the core seems to provide half the rate needed and I can't figure out for the life of me what I am doing wrong.

 

If anybody ran into this and can provide some insight I would highly appreciate it.

Thanks,

Amish

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Adventurer
Adventurer
2,861 Views
Registered: ‎04-08-2009

Although the fixed point "rate" input was puzzling, the output of the cic is correct. The issue was the clock going to it was not workign right.

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Adventurer
Adventurer
2,862 Views
Registered: ‎04-08-2009

Although the fixed point "rate" input was puzzling, the output of the cic is correct. The issue was the clock going to it was not workign right.

View solution in original post

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