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Contributor
Contributor
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Registered: ‎08-09-2020

there is a large violation between clkout2 and txoutclk_2 from PG235

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the video phy interface is PG230.

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ha4456 

Can you share a screenshot of part of your BD showing how the Video PHY and HDMI TX are connected?

Did you check that the connections were matching the example design?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

HI @ha4456 

Can you share your design? Without the design this is not really possible to tell what is wrong...

Are you using the Xilinx HDMI subsystem IP?

Did you check the HDMI example design? There is no timing failure there so it might be an issue with your design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ha4456 

 

Did you make sure fully path report at path 683 ?

According to summery report, it seems fine as total delay (logic delay (0.137 [ns]) and net delay (0.264 [ns]).

However, launched and captured clocks are different.

Does it need to synchronize them ?

 

If yes, I suggest you to add some constraint to resolve this issue.

 

- set_input_delay

  => add path delay constraint between two flip flops.

- Or, add location constraint. (Need to make sure fully path report to find proper location.)

 

If no, you try set_input_delay between two flip flops (Recommend) or set_false_path between two clocks (Not recommend).

If you don't know it, would you share the fully path report file at path 683.

 

Best regards,

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Contributor
Contributor
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Registered: ‎08-09-2020

Yes, i use the native interface(PG235+PG230 ).

the violation is only relative with (PG235+PG230 ).

 

do you mean to send the dcp file?

 

The launch and capture clock are difference.

 

 

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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ha4456 

 

Would you launch the following command on tcl console on Vivado ?

 

report_timing -from <your start point> -to <your end point> -setup -path_type full_clock_expand

 

If you want to know more details about report_timing command, refer UG835 at page 1439 or the following URL.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_1/ug835-vivado-tcl-commands.pdf#page=1439

 

Best regards,

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Contributor
Contributor
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Registered: ‎08-09-2020
 
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Teacher
Teacher
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Registered: ‎06-16-2013

Hi @ha4456 

 

I'm not sure whether this setup error is correct or pseudo.

But you might fix this error to change location of MMCME3_ADV, if possible.

=> Reduce clock net delay (4.698 + 4.702). The route cause is this clock net delay and it's related to location of MMCME3_ADV.

 

Best regards,

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Contributor
Contributor
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Registered: ‎08-09-2020

how to find which MMCME3_ADV is nearest?

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Contributor
Contributor
322 Views
Registered: ‎08-09-2020

the two clock can be set false path?

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @ha4456 

Can you share a screenshot of part of your BD showing how the Video PHY and HDMI TX are connected?

Did you check that the connections were matching the example design?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Contributor
Contributor
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Registered: ‎08-09-2020

I don't use BD.

 

It is RTL-based.

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Moderator
Moderator
183 Views
Registered: ‎11-09-2015

HI @ha4456 

Anyway, you should still start from the example design. You will see that there is no timing violation so it is probably a clock misconnected in your design or a constraint missing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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