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3,198 Views
Registered: ‎07-11-2011

using DUC and DDC in sysgen

Hi experts,

I am using xilinx12.4 version and imported DDC and DUC coregen IP cores to sysgen (MATLAB), i am unable to set proper input parameters to both of it. I read the dataseet of it but did not find discreption for some parameters.

Can anyone help me in understanding how to use it in my design.

Thanks

Ashwini

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Xilinx Employee
Xilinx Employee
3,164 Views
Registered: ‎08-01-2007

Are you using the DUC and DDC from CORE Generator, or are you using one of the DDC designs in the example directory?

Chris
Versal ACAP: AI Engines | Embedded SW Support

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