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Visitor
Visitor
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Registered: ‎08-25-2020

why retimer circuit is provided for HDMI TX lines?

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I am exploring a Zynq ultrascale+MPSoC designs, while glancing the reference design of XCZU9FFVB1156 SOC evaluation board, in HDMI interface there is retimer IC in the transmitter side of BAnk 128 which convert the HDMI signal to TMDS along and routed to HDMI output port. But in the receiver side there is no such signal enhancing or TMDS to HDMI circuit is used.

I have attached the snapshot of my observation from the evaluation board design for the reference.

Why there is no retimer or similar circuit in the HDMI input port?request you to clarify the concept.

Thanking you in advance

Regards Balkis

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Moderator
Moderator
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Registered: ‎11-09-2015

Hi @BM 

Xilinx recommends both a retimer and a re-driver as shown on the ZCU106 UG1244:

ZCU106.PNG

 

This is indeed because the GTs are not supporting directly the TMDS Level Signaling. This is mentioned in PG230:

The GT Receiver does not support TMDS Level Signaling and must be used with a retimer or equalizer to be compliant with the TMDS specification. While the system can work without aTMDS retimer, Xilinx does not provide recommendations on this and recommend that alldesigns use a TMDS retimer.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Guide
Guide
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Registered: ‎01-23-2009

I don't have a definitive answer, but the answer is almost certainly based on the HDMI compliance requirements. HDMI specifies the requirements for both a transmitter and receiver. From what you are seeing, the FPGA is able to receive HDMI data even if it is at the "worst" possible conditions allowed by the HDMI specifications. Conversely, the requirements on the HDMI output are probably too strict to allow them to be met by the FPGA's MGT directly; some characteristic of the required HDMI specification can't be met by the MGT directly. As a result, the solution is to have a retimer designed for HDMI be the actual driver of the TX on the HDMI cable.

Avrum

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Moderator
Moderator
367 Views
Registered: ‎11-09-2015

Hi @BM 

Xilinx recommends both a retimer and a re-driver as shown on the ZCU106 UG1244:

ZCU106.PNG

 

This is indeed because the GTs are not supporting directly the TMDS Level Signaling. This is mentioned in PG230:

The GT Receiver does not support TMDS Level Signaling and must be used with a retimer or equalizer to be compliant with the TMDS specification. While the system can work without aTMDS retimer, Xilinx does not provide recommendations on this and recommend that alldesigns use a TMDS retimer.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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Visitor
Visitor
351 Views
Registered: ‎08-25-2020

Thank you Florent for your reply.

 

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