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Explorer
Explorer
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Registered: ‎04-23-2013

AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hello,

I am trying to use AXI VDMA to stream a single line of 32-bit-aligned video-like 4224B data set to DMA RAM.

I am going by pg020 as a guide, and I am expecting the waveforms as in figure 2-2

 

I have the IP configured as:

write channel only

line buffer =512

fsync = s2mm_tuser

genlock = master

no unaligned transfer

 

I have my SOF connected to s2mm_tuser.

I read in a post that tkeep(3 downto 0) should be tied high, but I have tried both ways.

 

I am viewing these signals on a logic analyzer.

I have attached screenshots.

 

The 1st thing to notice in the signals is that tready is high from the beginning and only goes low after each write.

In figure 2-2 it shows that tready stays low until after tuser is pulsed.

 

No matter how much data I send it, the frame never advances.

 

I have tried everything I can think of.

Please help!

 

Thanks,

Emmett

 

Tags (3)
AXI_VDMA in block design.png
AXI_VDMA Basic.png
AXI_VDMA Advanced.png
pg020 figure 2-2.png
VDMA1.bmp
VDMA2A.bmp
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1 Solution

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Moderator
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Registered: ‎10-04-2017

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi @emmettbradford,


The VDMA transfers Video from a streaming interface to a mapped memory and also the other direction. (Mapped memory to stream) To get the VDMA to transfer data both the Streaming interface and Memory Mapped interface need to be connected. For more information, please refer to PG020.

http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_3/pg020_axi_vdma.pdf

 

If your goal is to buffer small amounts of video, you may want to take a look at creating a line buffer with a large FIFO.

 

The XAPP has a block design which shows the AXI VDMA pushing and pulling memory from a DDR3 interface. This is an older design, but as an overview it is helpful. (In the S2MM path there is an AXI interconnect which is not necessary if only 1 IP is accessing the Memory)

 

The Example design in PG020 does not have a block design, but it is newer. If you open up the elaborated design, it can make it simpler to see how the project is implemented. I believe it targets BRAM for the MM interface.

 

If you want to connect to the PS(processing system) memory. Take a look at the ZC702 TRD. I believe some of the other TRD’s implement the AXI VDMA as well. http://www.wiki.xilinx.com/Zc702+Base+TRD

 

-Sam

 

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Xilinx Video Design Hub
19 Replies
Moderator
Moderator
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Registered: ‎10-04-2017

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi @emmettbradford,

 

Can you provide a register dump for the VDMA core?

 

Thank you,

Sam

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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@emmettbradford

 

Is there any reason why you want to use s2mm tuser as fsync? In this mode, each frame only advances after next tuser arrives. Please try free run mode, and then see if you can get continuous tready.

 

The other thing you need to take care is the Hsize, which is based on the bytes, not pixels/line.

 

You can use TPG to drive S-AXIS_s2mm of VDMA to evaluate the VDMA behaviour. After you can make it work with TPG, then switch back to the real Video stream source of your design.

Explorer
Explorer
2,067 Views
Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi xud,

Thanks for the reply!

 

I changed to fsync=none and things look better.

Now the problem I'm seeing is that tready goes low before the frame is complete.

 

In the attached picture, I am trying to use a frame that is 1 line = 4224 Bytes.

The hsize limit is 16 bits or 65535?

I think the frame won't advance until it sees tlast?

 

 

My attached initialization follows what I found in xaxivdma.h

It may be in conflict with what is called for in pg020 pg 49.

I noticed that XAxiVdma_DmaConfig calls XAxiVdma_ChannelConfig which seems to write VSIZE before HSIZE.

 

 

 

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Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi Sam,

Thanks for the reply!

 

Is there a function for a register dump?

Or do I need to write code for that?

 

Thanks,

Emmett

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2007

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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@emmettbradford Yes, tlast(EOL, means end of line) should be asserted at the last pixel of each line.

 

In your case, data width is 32 bits = 4 bytes per pixel. I'm not sure 4224 is pixel/line or bytes/line, if it's pixel/line, you need to set Hsize to 4224*4 (decimal value)

Explorer
Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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xud,

AS you can see from the logic analyzer picture, tready goes low before tlast occurs.

I have the # bytes correct at 4224 bytes.

What could be the cause of this?

 

What about my initialization code?

Does it look OK?

 

Thanks,

Emmett

 

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Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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I tried initializing the registers directly instead of using the higher-level functions in xaxivdma.c et al.

I get the same result.

The tready line goes low before all the data is written.

Also, no data makes it to the store addresses.

 

Attached is my register dump.

It looks good to me.

 

Thanks,

Emmett

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Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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What about the line buffer?

Does it have to be any particular size?

When it says 512 w/ width 32, does that mean 2kB?

Thanks,

Emmett

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Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Apparently the line buffer has to be >= the size of a line!

I increased it to 2048 words = 8KB.

Now the entire frame is sent into the VDMA.

 

However, the frame is still not advancing and no data is written to RAM.

 

Please advise.

Thanks,

Emmett

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Adventurer
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Registered: ‎07-18-2011

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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One thing i see in the last image in your first post is that your tuser bit is going high for one clock (as it should) but tvalid is low during that time, so there is no tready/tvalid handshake for the SOF.

 

As for tready, it can go low anytime it wants to, because  tready signifies the slave is ready to accept data from the master.  If it is not ready, you cannot keep sending new data.   The master does not have to wait for tready to be high to put the first data on the bus, it can go ahead and put data out and pull tvalid high, but once it pulls tvalid high, the data must remain constant and tvalid must stay high until the slave pulls ready high to acknowledge a handshake and data transfer.

 

See to this webpage for an illustration of the ready/valid handshake for SOF:   https://lauri.võsandi.com/hdl/zynq/axi-stream.html

 

Refer to UG934 for more insight on AXI4-Stream video transfers.

 

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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi Reakin,

Thanks for the reply!

 

I was advised earlier in this thread to change to fsync=none.

Maybe I'll change it back to fsync=tuser and see what happens now.

 

I understand the purpose of tready.

I just didn't understand why it went low and never came back.

Now with larger line buffer, it stays high all the time.

This make me wonder why pg020 figure 2-2 shows it as it does.

 

Thanks,

Emmett

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Moderator
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Registered: ‎10-04-2017

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi @emmettbradford,

 

@reaiken, made an excellent observation about the necessary AXI handshake for SOF.

 


Fsync:


free run mode allows video data to be transferred as soon as possible without external triggers (s2mm fsync or s2mm tuser). (page 56 of PG020). If you change it back to tuser you will need to verify that your s2mm tuser signal is operating correctly.

 

 

Tready:


tready is able to assert if there is enough internal buffer space available, when that space is no longer available the core cannot be  "ready" to receive data. One of the most common reasons that it goes low is that data is not being transferred from internal buffer space out of the core, usually caused by backpressure from downstream or sizing conflicts.

 

 

Register Dump:


You did a good job of showing how you instantiated the core in your first post which shows a lot of the cores configuration. The VDMA contains registers that need to be set to allow it to operate correctly. Showing the configuration of these registers allows someone to see the full picture of your design and answer without making assumptions.

 

 

How to get a Register Dump.


There is not usually a built-in function for dumping the resisters as a whole. Most of the IP drivers include a function to read form each configuration register quickly and then display the results. In this case I believe the driver function is XAxiVdma_ReadReg(BaseAddress, RegOffset) which you can then send the results to xil_printf( const char8 *ctrl1, ...).

 

 

Generating a register dump is a small amount of upfront work but can make it much clearer what your intentions are and make it easier to help find the issue!

 

Can you provide your current register dump so that we can see the values being set for Hsize/Vsize/stride/address/control/interrupt... etc.

 

Thank you!

Sam

 

 

 

 

 

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Explorer
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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi Sam,

That's a lot of good insight.

I posted my register dump yesterday.

It looks good to me.

I am working on verifying a smaller frame now to make sure my counts are good.

Thanks,
Emmett

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Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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@emmettbradford

 

Have you measure the tready assertion time in waveform? How many cycles it asserts? Have you ever get tlast pulse in your design? Can you export ILA data, and then upload it, I will take a look.

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Registered: ‎10-04-2017

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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 Hi @emmettbradford,

 

I missed your register dump, thank you for posting it.

 

I see a few things.

You programmed your start addresses 1-16, and I am assuming you set 0x44 to 1 to program the other 16 registers as you set the configuration to 32 frame buffers.

 

You have Vsize set to 1. Is this for testing purposes? If not, it almost looks like you are using the VDMA as a line buffer, you might take a look at using a line buffer instead. The memory would be BRAM instead of DRAM. (AXI Stream FIFO PG085).

 

Have you tried a Vsize of 2+? Theoretically the VDMA should be able to handle a line size of 1, however, I have not tried it before.

 

What is the current status of your project? Is video data flowing into the core? Does video data come out of the core? How many lines are going in/out before there is an issue?

 

Also as Xud mentioned, your ILA data would be helpful.

 

-Samk

 

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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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HI Sam, Xud,

Thanks so much for your replies.

I am struggling with this.

 

I saw some discrepant comments in the BSP files about the max frame stores being 16 instead of 32.

Today I am using 8 just to be sure.

I attached today's VDMA register dump.

 

I don't have an ILA IP in my design, I probably should.

I have been using an external hardware logic analyzer.

 

I reduced my frame to 128 bytes = 32 stream-width words.

I count 32 transfers w/ tvalid high and tlast high on the last one. 

 

I did set this up for a linear image sensor, so VSIZE=1 was intentional.

 

I also tried converting everything to 4 lines * 32 bytes, VSIZE=4, HSIZE=32.

That also counted out correctly on my logic analyzer.

Still no success.

 

If I use fsync=tuser, I get SOF late error bit set in the status register.

If I use fsync=none, there are no errors indicated.

 

However, not matter what, s2mm_frame_ptr_out never advances, and no data is ever written to RAM.

Data is flowing into VDMA w/ no problem,

 

 

Since genlock mode = master, VDMA drives s2mm_frame_ptr_out - right?

 

 

 

Thanks,

Emmett

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Registered: ‎10-04-2017

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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Hi @emmettbradford,


The VDMA transfers Video from a streaming interface to a mapped memory and also the other direction. (Mapped memory to stream) To get the VDMA to transfer data both the Streaming interface and Memory Mapped interface need to be connected. For more information, please refer to PG020.

http://www.xilinx.com/support/documentation/ip_documentation/axi_vdma/v6_3/pg020_axi_vdma.pdf

 

If your goal is to buffer small amounts of video, you may want to take a look at creating a line buffer with a large FIFO.

 

The XAPP has a block design which shows the AXI VDMA pushing and pulling memory from a DDR3 interface. This is an older design, but as an overview it is helpful. (In the S2MM path there is an AXI interconnect which is not necessary if only 1 IP is accessing the Memory)

 

The Example design in PG020 does not have a block design, but it is newer. If you open up the elaborated design, it can make it simpler to see how the project is implemented. I believe it targets BRAM for the MM interface.

 

If you want to connect to the PS(processing system) memory. Take a look at the ZC702 TRD. I believe some of the other TRD’s implement the AXI VDMA as well. http://www.wiki.xilinx.com/Zc702+Base+TRD

 

-Sam

 

Don't forget to reply, kudo, and accept as solution.

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Explorer
Explorer
1,913 Views
Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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That was the problem!

The only example that seemed applicable was the ZC702 TRD.

I emulated that by adding another AXI Interconnect instance and connecting to the HP Slave port on the Zynq.

Now the frame is advancing!

 

I assume that means the data is going somewhere.

I'll figure out where next.

 

Thanks SamK, Xud, Reaiken!

Emmett

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Registered: ‎04-23-2013

Re: AXI VDMA s_axis_s2mm_tready not behaving as expected

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I forgot to add the screenshot of my bd, so others can see.

AXI_VDMA in block design 2.png
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