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769 Views
Registered: ‎10-09-2017

AXI Video signaling TUSER Not Propogating Thru AXI Data FIFO

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I am using Xilinx IP "AXI4-Stream Data FIFO". It is configured to have the TUSER signal on the slave AXI-streaming interface and also on the master AXI-streaming interface.
 
The AXI-Stream Data FIFO is between the AXI TPG and the AXI VDMA. Frame sync using the signal TUSER from the AXI TPG needs to get to the AXI VDMA through the AXI Data FIFO. 80% of the time, the TUSER arrives at the AXI VDMA with no problem. However, 20% of the time TUSER frame sync is generated by the AXI Data FIFO but it does not go active at the same time that TVALID=1, so the VDMA ignores it (as it should).
 
Is there a way to reliably pass VSYNC start-of-frame signaling as TUSER through an AXI Data FIFO?
 
Thanks!
John
 
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968 Views
Registered: ‎10-09-2017

Re: AXI Video signaling TUSER Not Propogating Thru AXI Data FIFO

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Hi Samk,

 

I revisited this issue to today to answer some of your questions. To my surprise I cannot reproduce the problem. The AXI Data FIFO is generating the TUSER output with the TVALID=1 for one clock, so all is working correctly. I'm not sure why today's results are different but further action is no longer necessary.

 

I am still having a frame sync issue. I thought it was due to the AXI Data FIFO, but now it turns out more likely to be an AXI TPG issue. Since this topic subject is about AXI Data FIFO, I think it would be best to open a new topic to discuss the subject of what the problem with AXI TPG could be.

 

Thanks!

John

 

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722 Views
Registered: ‎10-04-2017

Re: AXI Video signaling TUSER Not Propogating Thru AXI Data FIFO

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Hi jlevieux@a2etechnologies.com,

 

This sounds like a resolution mismatch or sizing issue.

 

Can you give us some details such as:

 

Clock frequency's to TPG, FIFO, VDMA?

Resolution settings for TPG, VDMA?

Size of the FIFO?

 

From the TPG PG:

Start of Frame Signals - m_axis_video_tuser0, s_axis_video_tuser0

The Start-Of-Frame (SOF) signal, physically transmitted over the AXI4-Stream TUSER0

 

signal, marks the first pixel of a video frame. The SOF pulse is 1 valid transaction wide, and

must coincide with the first pixel of the frame, as seen in Figure 2-7. The SOF signal serves

 

as a frame synchronization signal, which allows downstream cores to re-initialize, and

detect the first pixel of a frame. The SOF signal may be asserted an arbitrary number of

AP_CLK cycles before the first pixel value is presented on DATA, as long as a VALID is not

asserted.

 

Can you describe or add an ILA showing where the TUSER signal is being asserted in relation to the first pixel? (Both into and out of the FIFO)

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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969 Views
Registered: ‎10-09-2017

Re: AXI Video signaling TUSER Not Propogating Thru AXI Data FIFO

Jump to solution

Hi Samk,

 

I revisited this issue to today to answer some of your questions. To my surprise I cannot reproduce the problem. The AXI Data FIFO is generating the TUSER output with the TVALID=1 for one clock, so all is working correctly. I'm not sure why today's results are different but further action is no longer necessary.

 

I am still having a frame sync issue. I thought it was due to the AXI Data FIFO, but now it turns out more likely to be an AXI TPG issue. Since this topic subject is about AXI Data FIFO, I think it would be best to open a new topic to discuss the subject of what the problem with AXI TPG could be.

 

Thanks!

John