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Observer parithyila
Observer
338 Views
Registered: ‎04-09-2019

AXI interface for Displayport TX Subsystem - Native Video Interface

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Hi,

I have refered Native Video Interface page no 13 in the   PG199 document , if i see the blok diagram of Native Video Interface it says that  AXI Interconnect, HDCP controller and AXI Timer will be present only when HDCP is enabled, in my design i am not going to use HDPC. so AXI interconnect will be disabled, if it is disabled than how can i configure the displayport transmitter.

Is it necessary to configure the displayport transmitter ? or it will configured while generating the ip

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Scholar watari
Scholar
301 Views
Registered: ‎06-16-2013

Re: AXI interface for Displayport TX Subsystem - Native Video Interface

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Hi @parithyila 

 

I mention to you about some interfaces.

 

# AXI4 interface

This is fully interface which is defined by ARM.

 

# AXI4-lite

This is sub-set of AXI4 which is used in processor interface.

 

# AXI4 Stream

This is similer AXI4. But it's diffetent. It is defined by ARM and Xilinx to using streaming data.

 

In this case, as @florentw already mentioned, they are different.

At least, you need to implement AXI4 lite to access this IP by processor core.

 

Best regards,

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4 Replies
Scholar watari
Scholar
335 Views
Registered: ‎06-16-2013

Re: AXI interface for Displayport TX Subsystem - Native Video Interface

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Hi @parithyila 

 

At least, DP Tx needs AXI4 lite interface to access this IP by CPU and so on even if you use native video interface.

 

Best regards,

 

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Observer parithyila
Observer
318 Views
Registered: ‎04-09-2019

Re: AXI interface for Displayport TX Subsystem - Native Video Interface

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Hi, but in doc it said it will not be enabled then how can i use it.
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Moderator
Moderator
316 Views
Registered: ‎11-09-2015

Re: AXI interface for Displayport TX Subsystem - Native Video Interface

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Hi @parithyila,

There are 2 differents interfaces. The inteconnect mentioned in the doc is an interconnect inside the Displayport Subsystem IP. You do not really see it (unless you open the view inside the IP).

You can still use an interconnect between your processor and the AXI4-Lite interface. This would be completely different.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Scholar watari
Scholar
302 Views
Registered: ‎06-16-2013

Re: AXI interface for Displayport TX Subsystem - Native Video Interface

Jump to solution

Hi @parithyila 

 

I mention to you about some interfaces.

 

# AXI4 interface

This is fully interface which is defined by ARM.

 

# AXI4-lite

This is sub-set of AXI4 which is used in processor interface.

 

# AXI4 Stream

This is similer AXI4. But it's diffetent. It is defined by ARM and Xilinx to using streaming data.

 

In this case, as @florentw already mentioned, they are different.

At least, you need to implement AXI4 lite to access this IP by processor core.

 

Best regards,

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