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Visitor natfallow
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Registered: ‎06-09-2019

AXI4-Stream TVALID stuck low between VDMA and video output block

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Hello,

I'm trying to buffer a single frame of video using a VDMA block on a Trenz TE0712 board (artix-7 based development board), based on a few examples (specifically Numato's framebuffer example and Xilinx's standalone driver examples). 
 
My current configuration uses a MicroBlaze to write a test pattern directly to memory, with the VDMA using only the read channel. Initialisation goes without a hitch, and as far as I can tell the MicroBlaze is successfully writing to the correct memory zone, but the VDMA does not transfer any data over MM2S_AXIS to the video out IP. 
 
Checking with the ILA, it looks like the correct data is sitting on the TDATA bus, and the video out IP's TREADY signal is high, but TVALID is stuck low so no transfer occurs. 
 
waveform.png
 
I've tried checking the VDMA read channel status register using the XSCT tool, but as far as that is concerned things are running fine:
 
xsct% mwr 0x44a00004 0xFFFFFFFF
xsct% mrd 0x44a00004
44A00004:   00010000
 
I'm not sure what's causing this issue, as I'm unable to find any errors with the debugging tools, and most troubleshooting info online seems concerned with TREADY errors, not TVALID. My best guess is that there is a VDMA configuration error happening, but I cannot spot where. Here's my MicroBlaze application code:
 
#include <stdio.h>
#include "xil_printf.h"
#include "xparameters.h"
#include "xstatus.h"
#include "xil_exception.h"
#include "xil_assert.h"
#include "xaxivdma.h"
#include "xaxivdma_i.h"
#include "xuartlite_l.h"

#define MEMORY_BASE XPAR_MIG7SERIES_0_BASEADDR
#define MEMORY_HIGH XPAR_MIG7SERIES_0_HIGHADDR

#define HRES 720
#define VRES 720

u32 srcBuffer = (MEMORY_BASE  + 0x1000000);
u32 highAdd = (MEMORY_HIGH);

XAxiVdma InstancePtr;
XAxiVdma_DmaSetup ReadCfg;

void fill(u8 red, u8 green, u8 blue) {
int x, y;
u32 i = 0;

u8 *src=(u8 *) srcBuffer;

for (y=0; y < VRES; y++) {
for (x=0; x < HRES; x++) {
src[i++] = blue;
src[i++] = green;
src[i++] = red;
}
}
}

int main()
{
    int status;

    xil_printf("Begin main\r\n");
    xil_printf("Framebuffer base address: 0x%X\r\n", srcBuffer);
    xil_printf("Framebuffer high address: 0x%X\r\n", highAdd);
    xil_printf("beginning VDMA set up\r\n");

    status = run_frame_buffer(0, HRES, VRES);
    if (status != XST_SUCCESS) {
xil_printf("Failed to run framebuffer, status: 0x%X\r\n", status);
return XST_FAILURE;
}

    while(1) {
    //cycle_colors(); disabled until VDMA read sorted
    }

    return 0;
}

int run_frame_buffer(int device_id, int hsize, int vsize) {
int status;
XAxiVdma_Config *Config;

Config = XAxiVdma_LookupConfig(device_id);
if (!Config) {
xil_printf("No video DMA found for ID %d\r\n", device_id );
return XST_FAILURE;
}

/* Initialize DMA engine */
status = XAxiVdma_CfgInitialize(&InstancePtr, Config, Config->BaseAddress);
if (status != XST_SUCCESS) {
xil_printf("Configuration Initialization failed, status: 0x%X\r\n", status);
return status;
}

u32 stride = hsize * (Config->Mm2SStreamWidth>>3);

/* ************************************************** */
/*           Setup the read channel                   */
/*                                                    */
/* ************************************************** */
ReadCfg.VertSizeInput       = vsize;
ReadCfg.HoriSizeInput       = stride;
ReadCfg.Stride              = stride;
ReadCfg.FrameDelay          = 0;      /* This example does not test frame delay */
ReadCfg.EnableCircularBuf   = 1;      /* Only 1 buffer, continuous loop */
ReadCfg.EnableSync          = 0;      /* Gen-Lock */
ReadCfg.PointNum            = 0;
ReadCfg.EnableFrameCounter  = 0;      /* Endless transfers */
ReadCfg.FixedFrameStoreAddr = 0;      /* We are not doing parking */

status = XAxiVdma_DmaConfig(&InstancePtr, XAXIVDMA_READ, &ReadCfg);
if (status != XST_SUCCESS) {
xil_printf("Read channel config failed, status: 0x%X\r\n", status);
return status;
}

// Initially populate framebuffer with complete green
fill(0x00, 0xff, 0x00);

/* Set the buffer addresses for transfer in the DMA engine. This is address first pixel of the framebuffer */
status = XAxiVdma_DmaSetBufferAddr(&InstancePtr, XAXIVDMA_READ, (UINTPTR *) &srcBuffer);
if (status != XST_SUCCESS) {
xil_printf("Read channel set buffer address failed, status: 0x%X\r\n", status);
return status;
}
/************* Read channel setup done ************** */

/* ************************************************** */
/*  Start the DMA engine (read channel) to transfer   */
/*                                                    */
/* ************************************************** */

/* Start the Read channel of DMA Engine */

status = XAxiVdma_DmaStart(&InstancePtr, XAXIVDMA_READ);
if (status != XST_SUCCESS) {
xil_printf("Failed to start DMA engine (read channel), status: 0x%X\r\n", status);
return status;
}

xil_printf("DMA engine running");

/* ************ DMA engine start done *************** */

return XST_SUCCESS;
}
VDMA hw configuration:
VDMA_advanced.PNGVDMA_basic.PNG


And the video block design (m_axi_mm2s_aclk is 100 MHz, and aclk is 34 MHz):
vid_bd.PNG

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Moderator
Moderator
327 Views
Registered: ‎11-09-2015

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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HI @natfallow 

If you have a memory address error you need to check on the memory side. Possible root causes:

  • The memory is not accessible for some reason. The memory controller might not allow to access this address or the processor might use it (did you change the linker script as per my video series?)
  • The VDMA is not connected to the memory

You might want to add an ILA on the AXI4 interface going to memory and check why you cannot access it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
6 Replies
Moderator
Moderator
379 Views
Registered: ‎11-09-2015

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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Hi @natfallow 

This is indeed stange because the VDMA seems to be running as per bit 0 of the status register.

On thing I do not understand in your configuration is how you set the stride, can you explain this value:

u32 stride = hsize * (Config->Mm2SStreamWidth>>3);

I would look at the AXI4 interface with the memory to see if there are transactions happening there. Maybe the VDMA is stalled there.

I have wrote some examples using the VDMA as part as my video series. You can have a look as it can be useful to have a working starting point.

Example 3 of Video Series 26: Examples of advanced uses of the AXI VDMA IP is pretty much what you are trying to do


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor natfallow
Visitor
345 Views
Registered: ‎06-09-2019

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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Hi @florentw,

Thanks for the response. I'm still trying to get this to work, and have tried shifting from a soft TPG to a more standard TPG IP & triple buffer VDMA, in case that helped. Unfortunately, problems are persisting, though not the same exact ones. To quickly answer your question: the stride being set in that way was from the Numato example I mentioned - I first used u32 stride = hsize * 3, but had quickly tried the other approach in case there was something I missed about it.

I have set up the TPG and VDMA similarly to that in the video series 24 example, with some modification for my hardware:

#define MEM_BASE XPAR_MIG7SERIES_0_BASEADDR

/* Start of VDMA Configuration */ /* Configure the Write interface (S2MM)*/ // S2MM Control Register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x8B); //S2MM Start Address 1 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, MEM_BASE + 0x02000000); //S2MM Start Address 2 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, MEM_BASE + 0x04000000); //S2MM Start Address 3 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, MEM_BASE + 0x06000000); //S2MM Frame delay / Stride register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, 720*3); // S2MM HSIZE register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 720*3); // S2MM VSIZE register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 720); /* Configure the Read interface (MM2S)*/ // MM2S Control Register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x8B); // MM2S Start Address 1 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, MEM_BASE + 0x02000000); // MM2S Start Address 2 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, MEM_BASE + 0x04000000); // MM2S Start Address 3 Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, MEM_BASE + 0x06000000); // MM2S Frame delay / Stride register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, 720*3); // MM2S HSIZE register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, 720*3); // MM2S VSIZE register Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 720);

But I am now getting a memory address error (0x00010041 on the VDMASR register), though I'm not sure where this could be arising. Both VDMA channels are configured to allow unaligned transfers, so I do not believe that is the issue.

Do you have any suggestions for other places to check? Thank you!

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Moderator
Moderator
328 Views
Registered: ‎11-09-2015

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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HI @natfallow 

If you have a memory address error you need to check on the memory side. Possible root causes:

  • The memory is not accessible for some reason. The memory controller might not allow to access this address or the processor might use it (did you change the linker script as per my video series?)
  • The VDMA is not connected to the memory

You might want to add an ILA on the AXI4 interface going to memory and check why you cannot access it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor natfallow
Visitor
298 Views
Registered: ‎06-09-2019

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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Hi Florent,

I've solved the memory issues with your suggestions of looking at the AXI memory streams with the ILA, and the video series examples, so I have accepted the solution.

I am still having issues with getting the output to work - having checked with the ILA, it appears the AXI-Stream to vid out was failing to lock, and the cause is the VTC EOL leading. This is very strange because the VTC is configured to default to the correct timing values as shown below, and in earlier tests I had no problems with this.

vtc.PNGtiming wrong.PNG

But the ILA shows that despite this configuration, the VTC is now outputting the timing for 640x480p video, including incorrect vsync and hsync polarities. I'm currently re-synthesising to add an AXI control interface to the VTC so I can force it to the correct configuration, but do you have any ideas why it would be reverting to 640x480p?

As an additional question: I am next wanting to read the buffered video with multiple VDMA read channels. Am I right to guess that for each additional read channel, I will need two more frame buffers, or can multiple VDMA read the same frame simultaneously? Happy to move these questions to a new thread if preferred.

Thanks again!

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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@natfallow wrote:

Hi Florent,

But the ILA shows that despite this configuration, the VTC is now outputting the timing for 640x480p video, including incorrect vsync and hsync polarities. I'm currently re-synthesising to add an AXI control interface to the VTC so I can force it to the correct configuration, but do you have any ideas why it would be reverting to 640x480p?

[Florent] - This is weird. I would expect the VTC to work with the custom resolution. Are you sure you using the correct bitstream?

As an additional question: I am next wanting to read the buffered video with multiple VDMA read channels. Am I right to guess that for each additional read channel, I will need two more frame buffers, or can multiple VDMA read the same frame simultaneously? Happy to move these questions to a new thread if preferred.

[Florent]  - I am not sure. It might be working to have multiple VDMA reading the same frame as long as there is no right happening at the same time (you will need to sync with the VDMA write with all the VDMA read). However, it might not be efficient. Did you consider using an AXI Broadcaster after the VDMA read to duplicate the output?

Regards

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Visitor natfallow
Visitor
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Registered: ‎06-09-2019

Re: AXI4-Stream TVALID stuck low between VDMA and video output block

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I resolved the VTC issue - I found the synthesis step was always using a cached version of the IP despite having updated the configuration. Clearing the cache fixed the problem and I'm now getting a reliable lock.

My aim with the multiple VDMA buffer is to have each crop a different segment of the incoming video frame (similar to the example in video series 26). Thank you for bringing up the AXI broadcaster, I think an easier approach may be to use that to split the input stream into multiple VDMA, each with read/write channels and three buffers, though this might overly congest the memory access. 

Thank you again for your help.