cancel
Showing results for 
Search instead for 
Did you mean: 
224 Views
Registered: ‎03-03-2017

CSI-2 RX dynamic linerate

Jump to solution

I am currently using Vivado/Vitis 2019.2 and have implemented CSI-2-RX successfully working with a custom CSI source that has variable CSI lane rate up to 2.5Gbps.   I have verified that with the CSI-RX block setup for 2.5Gbps and implemented that I can successfully get video working.   What I find strange is that the documentation specifies that dynamic linerate is not supported, but if I lower the custom hardware linerate I continue to successfully get video through.   It is as-if the CSI-RX is implemented with an upper limit, and all linerates below that work as well.

Can somebody confirm that this is the case?   The linerate specified in the CSI-RX block in the block design, is it just an upper limit?

Thanks.

Tim

Tags (2)
1 Solution

Accepted Solutions
Highlighted
Xilinx Employee
Xilinx Employee
201 Views
Registered: ‎03-30-2016

Re: CSI-2 RX dynamic linerate

Jump to solution

Hello Tim

>The linerate specified in the CSI-RX block in the block design, is it just an upper limit?

No.
I think PG232/PG202 is clearly mentioned that dynamic line-rate is not supported.

>Can somebody confirm that this is the case?   

If you set MIPI CSI-2 RX line-rate=2500Mbps in the GUI,

MIPI CSI-2 RX may work with input signal with lower line-rate=2400Mbps or even 2300Mbps, but, It will not work with 500Mbps.
The reason is MIPI D-PHY RX IP has a different clock architecture, depends on line-rate setting.

 

So, Xilinx recommends setting the exact line-rate on the GUI to match TX/sensor output line-rate.
If you find a slightly modified input clock-rate is working for you, please do a HW verification before using it on your product.

Thanks & regards
Leo

View solution in original post

4 Replies
Highlighted
Xilinx Employee
Xilinx Employee
202 Views
Registered: ‎03-30-2016

Re: CSI-2 RX dynamic linerate

Jump to solution

Hello Tim

>The linerate specified in the CSI-RX block in the block design, is it just an upper limit?

No.
I think PG232/PG202 is clearly mentioned that dynamic line-rate is not supported.

>Can somebody confirm that this is the case?   

If you set MIPI CSI-2 RX line-rate=2500Mbps in the GUI,

MIPI CSI-2 RX may work with input signal with lower line-rate=2400Mbps or even 2300Mbps, but, It will not work with 500Mbps.
The reason is MIPI D-PHY RX IP has a different clock architecture, depends on line-rate setting.

 

So, Xilinx recommends setting the exact line-rate on the GUI to match TX/sensor output line-rate.
If you find a slightly modified input clock-rate is working for you, please do a HW verification before using it on your product.

Thanks & regards
Leo

View solution in original post

Highlighted
152 Views
Registered: ‎03-03-2017

Re: CSI-2 RX dynamic linerate

Jump to solution

@karnanl ,

   Ok thanks for the confirmation that it should not work.  
   Strangely when I implemented with 2.5Gbps it worked when my hardware was setup for 2.5Gbps, but it continued working even when my hardware was setup for 1Gbps.   
   I can also confirm that when I implemented for 2Gbps it worked when my hardware was setup for 2Gbps, but stopped working as soon as I went above 2Gbps.   It also worked here down to 1Gbps.  
   This is why I suspect the Gbps selected in the IP appears to be an upper limit.   
   This is just information I have seen.  I understand this is not officially supported though.  
Thanks.  
Tim

Highlighted
Contributor
Contributor
109 Views
Registered: ‎12-27-2018

Re: CSI-2 RX dynamic linerate

Jump to solution

Dear Tim

 

It is funny that I see the same result.

My MIPI RX set line-rate as 756Mbps, sensor using same line-rate is working off course.

It is works fine too with line-rate 654Mbps. I do not see any issue at all.

But I found it is not work with TX with line-rate output 150Mbps.

 

Perhaps there is an upper limit and lower limit for each line-rate setting, so would be helpfull when Xilinx can make additional guide on this.

 

Best regards.

0 Kudos
Highlighted
Moderator
Moderator
101 Views
Registered: ‎11-09-2015

Re: CSI-2 RX dynamic linerate

Jump to solution

Hi @yuko.2828 

There will not be any guidance from Xilinx on this. Xilinx does not support dynamic line rate. So Xilinx only says that it will work with the line rate you are setting on the GUI.

If you are going over this line rate, then you are basically on your own. You have to do your own characterization. Xilinx do not comment on things that are not supported.

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**