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Explorer
Explorer
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Registered: ‎07-05-2017

Chroma Resampler 444 to 422

Hi,

My orignial design was based on an RGB format converted to RGBtoYcrYcb (YUV 444) then to YUV 422 and was able to stream the video out to an HDMI port on a Zedboard.

The issue is  Chroma Resampler IP to convert YUV 444-> YUV 422 evalustion license is about to expire and Xilinx FAE tells me this core is no longer available for purcahse. I was told to use the VPS IP core. I looked at the VPS (Video Processing System) IP core and did not find a Chroma Resampling YUV 444 -> 422  configuration. The one that exists is the YUV 422 -> 444 chroma upsampling configuration. This option will not work on the Zedbaord which uses the ADV7511 and it is configured to take YUV 422 (16 bits). I have looked at the Video Beginner Series 12: Using the AXI4-Stream Video Series 12Looking though similar discussions the author stated that VPSS can be used to Chroma resample 444 to 422 or just using a subset converter to do this function. I tried it but it did not work. 

Here is what I tried using a Test Pattern Generator and the results I'm getting.

Just to test the concept, put a TPG, Test Pattern Generator (YUV422) -> Axi Stream Subset Converter -> Axi Stream to Video out (Video format YUV422)-> ADV7511 (zedboard) and wrote a 0x1(YUV 422) to register 0x40 of the TPG gnerator. I see video being displayed. Then, I wrote a 0x0(RGB) to register 0x40 of the TPG gnerator and the output colors were all wrong as expected. 

 I made another test design run using: TPG, Test Pattern Generator  ->  Color Space Converter RGBtoYCrCb -> 444 to 422 Chroma Resampler (IP about to expire)->  Axi Stream to Video out (YUV422 fromat)-> ADV7511 and wrote a 0x0(RGB) to register 0x40 of the TPG gnerator. The design worked with proper colors as expected.

My question is: Since my design generates RGB video and I need to send it out in YUV422 fromat to the ADV7511 display controller on the Zedboard, what should I use for the Chroma Resampler IP 444 to 422 replacement?

 

Thanks!

 

 

 

 

 

 
 
 
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

Hi @aynilian 

You need to read more of my video series ;)

In the latest Video Series 28: Using the VPSS IP in Color Space Converter mode, I showed how to use the VPSS to do color space conversion.

The VPSS IP can do any video format to any video format, meaning that it can do YUV444 to YUV422 but also YUV422 to YUV444

In the example of this video series, you can change the input type (configured in the TPG) and the output is always YUV422.

Remember to give a kudos if a vidoe series was helpful to you ;)

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florentw,

Thanks for your reply.

Presently I have looked at your Video Series number 28 and I see that you are programing the register in the Video Processing System IP in Color Space Converter mode and setting the stream input as RGB and Stream output as YUV 422. I am trying to work around your desing using the Zedboard instead (See block Desing attached). I have modified the Video ouptut resolution to 1920 x 1080. It is not  working  yet even though I do get the Video datea h_sync and v_sync coming out the the HDMI chip. My display is displaying a message stating " HDMI Signal Out of Range Resolutin or Refresh Rate Not Supported). 

In step with your design, I put 

100 MHz -> TPG, VPSS, Subset Conveter, aclk of Axi Stream to Video Out.

40 Mhz -> VTC and Video output clk of Axi Stream to Video Out. (Before I usually would run this clock at 148.5 MHz). 

Similar to your design which seems to have 2 clocks. 100 MHz, 40 MHz 

100 MHz ->  TPG, VPSS, Subset Conveter, VDMA, Axi Smart Connect and aclk of Axi Stream to Video Out.

40 Mhz -> VTC and Axi Stream to Video Out.

 

I will let you know when the attached Block Design works. 

 

Note since my II2C for the ADV7511 is connected to differnt pins on the Zed board, I could not use your PS II2C interface. Here is  my modified C code.

 

:

int main()
{
init_platform();

demo.uBaseAddr_IIC_HdmiOut = XPAR_ZED_HDMI_IIC_0_BASEADDR;
zed_hdmi_display_init( &demo );

 


Status = XV_tpg_Initialize(&tpg_inst, XPAR_V_TPG_0_DEVICE_ID);
if(Status!= XST_SUCCESS)
{
xil_printf("TPG configuration failed\r\n");
return(XST_FAILURE);
}


// Set Resolution to 1920x1080
XV_tpg_Set_height(&tpg_inst, 1080);
XV_tpg_Set_width(&tpg_inst, 1920);

// Set Color Space to YUV420
//XV_tpg_Set_colorFormat(&tpg_inst, 0x3);


// Set Color Space to YUV422
//XV_tpg_Set_colorFormat(&tpg_inst, 0x2);

// Set Color Space to YUV444
//XV_tpg_Set_colorFormat(&tpg_inst, 0x1);


// Set Color Space to RGB
XV_tpg_Set_colorFormat(&tpg_inst, 0x0);


XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_COLOR_BARS);
//XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_CHECKER_BOARD);
// XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_DP_COLOR_SQUARE);
// XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_RAINBOW_COLOR);
//XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_TARTAN_COLOR_BARS);


// Set Overlay to moving box
// Set the size of the box
XV_tpg_Set_boxSize(&tpg_inst, 250);
// Set the speed of the box
XV_tpg_Set_motionSpeed(&tpg_inst, 5);
// Enable the moving box
XV_tpg_Set_ovrlayId(&tpg_inst, 1);

 


//Start the TPG
XV_tpg_EnableAutoRestart(&tpg_inst);
XV_tpg_Start(&tpg_inst);
xil_printf("TPG started!\r\n");


/* VPSS Configuration*/

VprocCfgPtr = XVprocSs_LookupConfig(XPAR_V_PROC_SS_0_CSC_DEVICE_ID);
XVprocSs_CfgInitialize(&VprocInst, VprocCfgPtr, VprocCfgPtr->BaseAddress);

//Get the resolution details
resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_60HZ, 0);
//resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_30HZ, 0);
TimingPtr = XVidC_GetTimingInfo(resId);

//Set the input stream
StreamIn.VmId = resId;
StreamIn.Timing = *TimingPtr;
StreamIn.ColorFormatId = colorFmtIn;
StreamIn.ColorDepth = VprocCfgPtr->ColorDepth;
StreamIn.PixPerClk = VprocCfgPtr->PixPerClock;
StreamIn.FrameRate = XVIDC_FR_60HZ;
StreamIn.IsInterlaced = 0;
XVprocSs_SetVidStreamIn(&VprocInst, &StreamIn);

//Set the output stream
StreamOut.VmId = resId;
StreamOut.Timing = *TimingPtr;
StreamOut.ColorFormatId = XVIDC_CSF_YCRCB_422;
StreamOut.ColorDepth = VprocCfgPtr->ColorDepth;
StreamOut.PixPerClk = VprocCfgPtr->PixPerClock;
StreamOut.FrameRate = XVIDC_FR_60HZ;
StreamOut.IsInterlaced = 0;
XVprocSs_SetVidStreamOut(&VprocInst, &StreamOut);

Status = XVprocSs_SetSubsystemConfig(&VprocInst);
if(Status!= XST_SUCCESS)
{
xil_printf("VPSS failed\r\n");
return(XST_FAILURE);
}
xil_printf("VPSS Started\r\n");

/* Endf of VPSS configuration */

:

:

:

 

 

tpg_vpss.png
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florentw,

Thanks for your reply.

Presently I have looked at your Video Series number 28 and I see that you are programing the register in the Video Processing System IP in Color Space Converter mode and setting the stream input as RGB and Stream output as YUV 422. I am trying to work around your desing using the Zedboard instead (See block Desing attached). I have modified the Video ouptut resolution to 1920 x 1080. It is not  working  yet even though I do get the Video datea h_sync and v_sync coming out the the HDMI chip. My display is displaying a message stating " HDMI Signal Out of Range Resolutin or Refresh Rate Not Supported). 

In step with your design, I put 

100 MHz -> TPG, VPSS, Subset Conveter, aclk of Axi Stream to Video Out.

40 Mhz -> VTC and Video output clk of Axi Stream to Video Out. (Before I usually would run this clock at 148.5 MHz). 

Similar to your design which seems to have 2 clocks. 100 MHz, 40 MHz 

100 MHz ->  TPG, VPSS, Subset Conveter, VDMA, Axi Smart Connect and aclk of Axi Stream to Video Out.

40 Mhz -> VTC and Axi Stream to Video Out.

 

I will let you know when the attached Block Design works. 

 

Note since my II2C for the ADV7511 is connected to differnt pins on the Zed board, I could not use your PS II2C interface. Here is  my modified C code.

 

:

int main()
{
init_platform();

demo.uBaseAddr_IIC_HdmiOut = XPAR_ZED_HDMI_IIC_0_BASEADDR;
zed_hdmi_display_init( &demo );

 


Status = XV_tpg_Initialize(&tpg_inst, XPAR_V_TPG_0_DEVICE_ID);
if(Status!= XST_SUCCESS)
{
xil_printf("TPG configuration failed\r\n");
return(XST_FAILURE);
}


// Set Resolution to 1920x1080
XV_tpg_Set_height(&tpg_inst, 1080);
XV_tpg_Set_width(&tpg_inst, 1920);

// Set Color Space to YUV420
//XV_tpg_Set_colorFormat(&tpg_inst, 0x3);


// Set Color Space to YUV422
//XV_tpg_Set_colorFormat(&tpg_inst, 0x2);

// Set Color Space to YUV444
//XV_tpg_Set_colorFormat(&tpg_inst, 0x1);


// Set Color Space to RGB
XV_tpg_Set_colorFormat(&tpg_inst, 0x0);


XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_COLOR_BARS);
//XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_CHECKER_BOARD);
// XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_DP_COLOR_SQUARE);
// XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_RAINBOW_COLOR);
//XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_TARTAN_COLOR_BARS);


// Set Overlay to moving box
// Set the size of the box
XV_tpg_Set_boxSize(&tpg_inst, 250);
// Set the speed of the box
XV_tpg_Set_motionSpeed(&tpg_inst, 5);
// Enable the moving box
XV_tpg_Set_ovrlayId(&tpg_inst, 1);

 


//Start the TPG
XV_tpg_EnableAutoRestart(&tpg_inst);
XV_tpg_Start(&tpg_inst);
xil_printf("TPG started!\r\n");


/* VPSS Configuration*/

VprocCfgPtr = XVprocSs_LookupConfig(XPAR_V_PROC_SS_0_CSC_DEVICE_ID);
XVprocSs_CfgInitialize(&VprocInst, VprocCfgPtr, VprocCfgPtr->BaseAddress);

//Get the resolution details
resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_60HZ, 0);
//resId = XVidC_GetVideoModeId(Width, Height, XVIDC_FR_30HZ, 0);
TimingPtr = XVidC_GetTimingInfo(resId);

//Set the input stream
StreamIn.VmId = resId;
StreamIn.Timing = *TimingPtr;
StreamIn.ColorFormatId = colorFmtIn;
StreamIn.ColorDepth = VprocCfgPtr->ColorDepth;
StreamIn.PixPerClk = VprocCfgPtr->PixPerClock;
StreamIn.FrameRate = XVIDC_FR_60HZ;
StreamIn.IsInterlaced = 0;
XVprocSs_SetVidStreamIn(&VprocInst, &StreamIn);

//Set the output stream
StreamOut.VmId = resId;
StreamOut.Timing = *TimingPtr;
StreamOut.ColorFormatId = XVIDC_CSF_YCRCB_422;
StreamOut.ColorDepth = VprocCfgPtr->ColorDepth;
StreamOut.PixPerClk = VprocCfgPtr->PixPerClock;
StreamOut.FrameRate = XVIDC_FR_60HZ;
StreamOut.IsInterlaced = 0;
XVprocSs_SetVidStreamOut(&VprocInst, &StreamOut);

Status = XVprocSs_SetSubsystemConfig(&VprocInst);
if(Status!= XST_SUCCESS)
{
xil_printf("VPSS failed\r\n");
return(XST_FAILURE);
}
xil_printf("VPSS Started\r\n");

/* Endf of VPSS configuration */

:

:

:

 

 

tpg_vpss.png
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Moderator
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720 Views
Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

Hi @aynilian 

My design was build for a video resolution 800x600, this is why the video clock is 40MHz ( see 800x600@60Hz). If you need to support a different resolution you need to make sure you are doing all the required changes. Among them, you need to change the video clock to 148.5MHz if you need 1920x1080.

You will also need to configure the VTC to generate the correct timing.

Without this I am not surprise your design is not working.

All of this was explained in my Video Series 22: Supporting multiple video resolutions on ZC702 HDMI


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

Do you have any update on this? Were you able to make the design working?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florent

Back from my vacation.

I read your Video series 22 and tried to generate the project using TCL, the automatic wire generation did not connect all the modules together in the BD. I'm Not sure what clock rate you have the VPSS module and the rest of the aclks running at?

On my design  I tried the clock changes and rechecked the VTC configuration. Now I'm getting Underflow flag toggling.

The clock connections are:

TPG ap_clk = 150 MHz

VPS aclk = 150 MHz

Axi subsystem converter aclk = 150 MHz

Axi4 Stream to Video out aclk = 150 MHz.

Axi4 Stream to Video out vid_io_out_clk = 148.5 MHz.

VTC clk = 148.5 MHz

 

Here is the attached blcok diagram of my design. I will try to increase the 150 MHz to higher frequency see when the underflow flag goes away.

 

Will let you posted.

 

Thanks,

 

 

 

 

2019-08-01_0723_vtc1.png
2019-08-01_0724_vtc2.png
2019-08-01_0725_videostream.png
2019-08-01_0728_vpss422.png
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Moderator
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

To build the design you need to make sure you are using 2018.3.

Then the main difference with my design is that my design includes a VDMA which can do buffering. Adding at least a FIFO after the VPSS might help.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florent,

 

I'm using 2018.3 for all the desings.

 

I upped the clock to 200 MHz in the Zynq (actual 187.5 MHz) that connects to all the aclk's on the TPG, VPSS ...

The video_out_clock is still 148.5 Mhz. I'm still getting Underflow flag going active from the output of the Video Stream Converter. This is very strange!

As for adding a FIFO after the VPSS, The Video Stream Converter already has 1024 deep Fifo. If the subset converter is ignored which is just doing bus width conversion from 24 to 16, the FIFO is after the VPSS. 

Do you just suggest adding a FIFO between the VPSS and the SUBSET Converter and use the FIFO Almost Full Flag as Tready to the VPSS and the Tready from the Subset converter to the Read Enable of the FIFO?

 

Thanks,

Aynilian

 

 

 

2019-08-02_0949_video_stream.png
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

I recommend you to add some ILAs to check what IP is not sending data.

Do you just suggest adding a FIFO between the VPSS and the SUBSET Converter and use the FIFO Almost Full Flag as Tready to the VPSS and the Tready from the Subset converter to the Read Enable of the FIFO?

No I do not think this would help


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

HI Florent

 

I tried many permutations of this design, I put the aclks up to 250 Mhz with no success. I still see underflows on the output of the Video Stream Converter. I increased the FIFO depth of the Video Stream Converter to 4096 and had the same underflow issue. Now I put the aclks to 166 MHz and the Video_clock_out to 148.5 MHz added an AXI Stream FIFO and ILAs ans till same underflow issue.

Here is a section of the Design with ILAs and also an AXI Stream FIFO between the Sunbset Converter and Video Stream Converter. I also added a counter to count the number of Pixels being input to the Video Stream converter between frames using TVALID and TLAST, but seems like the active low CE that I tied to inverted TVALID fome the Fifo did not enable the counter. The SCLR on the counter may be wrong polarity. I've seen these many times, the Inverter bubbel in the IP diagram is not always true indication of active low or active high status, so I will try to take out the inverter in the next design run.

I see DATA and Controls going into the Video Stream Converter. Also I see VTC video timing pulses going into the Video Stream converter, but I still see underflow flag going active in the Video Stream converter output.

I have attached most of the ILA captures connecterd to the input and output of the Video Stream Converter.

 

 

2019-08-05_0831_Fifo_data_control.png
2019-08-05_0840_ILA_from_SUBSET_FIFO_Vide_Stream.png
2019-08-05_0851_VTC_Timing.png
2019-08-05_0900_Video_Stream_Undeflow.png
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

I am surprised you are still getting an underflow signal while we can clearly see that the data is continuously coming into the AXI4S to video out IP.

Maybe you are incorrect of the polarity of a clock_en signal?

Can you also check the Status output of the AXI4S to video out IP? Then you can refer  to Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florent,

1. Just to confirm that the stream that is being clocked in to the Video Stream Converter  is 1920 Columns by 1080 Lines, I inserted two counters and confirmed that 1920 by 1080 are being clocked in. I have attached the proof in the ILA capture.

2. Clock Enable of the Video Stream Converter is tied High High -> aclken. to prove this I have attached a diagram of the aclken constant level state. I have also verified the VTC generating Hsync, Vsync and blanking signals.

At the moment I can't think of anything else that could be causinbg the Underflow condition. Will go thourugh your Video Series 8 and see if that sheds any light in this issue.

Thanks,

2019-08-06_1005_line_pixel_length.png
2019-08-06_1006_line_colum_counts.png
2019-08-06_1011_whole_block.png
2019-08-06_1023_aclken_high.png
2019-08-06_1024_constan_1.png
2019-08-06_1051_vtc.png
Moderator
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

Were you finally able to make progress on this?

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florent,

I tried looking at the Status bits from the Video Stream Converter by connecting them to an ILA probe, but after place and route I programmed the FPGA I could not see the status bits in the ILA.

Instead of using the Video Stream Converter, I am writing my own RTL code to take in the Video Stream into a FIFO and send it out to HDMI with the Hsync and Vsync timing translated from the VTC. I will let you know the results.

Thanks!

Aynilian

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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florentw,

I finished writing an RTL code and replaced the Axi Stream to Video output IP in the design which was generating underflow flag and no HDMI Video output. I just tested the RTL with the VPSS in Chroma RGB to YUV422 conversion mode and I see proper HDMI output video. Below are the Video and  block digarams of the modified poriton of the Video AXI Stream to Video Output RTL module Block. Thanks for your suggestions.

If anyone has similar issue I can share the RTL.

Thanks,

Aynilian

 

 

20190826_152416_Film2.jpg
axi_to_to_vid_rtl.PNG
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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

If you have an underflow, I would suggest adding a VDMA. This would help repeating frames if you do not have enough data coming in.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎07-05-2017

Re: Chroma Resampler 444 to 422

Hi Florentw,

From my post in this thread on 8/6/19, I put a column and line counters on the Data line coming in to the Axi Video Stream converter. It counted 1920 by 1080.  With the correct data column and line widths, the design was still getting underflows.  This is why I think there is something peculiar with the Xilinx's Axi Stream to Video IP which prompted me to replace it with an RTL module.

In a previeous desgin, where I had used the Axi Stream to Video IP with a VDMA and Chroma Resampler IP (obsolete), the design had worked. Your suggestion of using a VDMA may do the trick by regenerating frames for underflow conditions. Note: could it be that I'm using the VPSS instead of Chroma Resempler IP that is causing some unknown issues with underflow? In any case, I will try the VDMA again but this time using the VPSS as a replacement for the Chroma Resampler IP. This was my next step in my project development anyway. Will let you know.

Thanks!

Aynilian

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Registered: ‎11-09-2015

Re: Chroma Resampler 444 to 422

HI @aynilian 

If there is an underflow signal in the AXI4-Stream to Video out, it usually means that there is no enough data not that there is an issue with the data. So yes I am pretty sure a VDMA could help


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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