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Observer peterjuteoa
Observer
314 Views
Registered: ‎04-02-2019

Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

Hi,

We are developing video H/W accrelatation using ZCU104 board and choose 2018.3 version reVISION reference design (signle sensor) as our reference design platform.

We want to drive special resolution 1440x2560 HDMI output (sink), however, we found it can't be straight away to run gst-launch command at high level to get it work.

We invetigated and found:

1) After image boot, two LEDs (HDMI tx locked and HDMI tx hb) on hardware board doesn't work

2) Linux debug information (modetest and a0080000.hdmi_txss) show kernel dosn't recognize this 1440x2560 resolution.

We thought it is linux kernerl (driver) issue and we changed something in kernel (such as drm_edid.c and mixer.c, etc) to add customer resolution in CEA/drm list to support and use petalinux to rebulid new linux image.

We implemented new image again and HDMI tx locked LED is still in OFF state but tx hb is flicking now. For the kernel, we can see customer resolution in the a0080000.hdmi_txss:

Color Format: RGB
Color Depth: 8
Pixels Per Clock: 2
Mode: Progressive
Frame Rate: 50Hz
Resolution: 1440x2560 [Custom Mode]
Pixel Clock: 204792000

HSYNC Timing: hav=1440, hfp=70, hsw=35(hsp=0), hbp=045, htot=1590
VSYNC Timing: vav=2560, vfp=12, vsw=02(vsp=0), vbp=002, vtot=2576

but it still can't driver 1440x2560 LCD panel.

How can I do to make the panel work and what's other solution for it (we still want to keep use zcu104 revision platform).

 

Thanks,

Peter

 

   

 

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8 Replies
Xilinx Employee
Xilinx Employee
251 Views
Registered: ‎08-02-2007

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

@peterjuteoa 

If HDMI tx locked is LOW, that means there is issue with Video Timing driven to HDMI TX.

That lock signal is from AXI4-Stream to Video Out IP, which is a sub-module if you use AXI4 Stream Video interface for HDMI TX Subsystem IP.

It tries to synthronous the video timing between AXI4 Streaming Data and the timing generated by VTC. If both of them are correct, then it asserts lock.

Please let me know how you generate the video pattern, and drive it to HDMI TX.

 

Observer peterjuteoa
Observer
230 Views
Registered: ‎04-02-2019

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

Hi,

1. We modified the kernel file https://github.com/Xilinx/linux-xlnx/blob/master/drivers/gpu/drm/drm_edid.c,

add new resolution in static const struct drm_display_mode drm_dmt_modes[] = {}

/* 0x59 - 1440x2560@50Hz 16:9 */ //customer size
{ DRM_MODE("1440x2560", DRM_MODE_TYPE_DRIVER, 204792, 1440, 1510,
1545, 1590, 0, 2560, 2572, 2574, 2576, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },

Also add new resolution in static const struct drm_display_mode edid_cea_modes[] = {}

/* 108 - 1440x2560@50Hz 16:9 */ //customer size
{ DRM_MODE("1440x2560", DRM_MODE_TYPE_DRIVER, 204792, 1440, 1510,
1545, 1590, 0, 2560, 2572, 2574, 2576, 0,
DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
.vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE, },

And rebuild the kernel

 

2. We already proved HDMI TX timing which is for VTC was verified and passed on HDMI_TXSS EXAMPLE design by using same ZCU104 revision board and vivado 2018.3, that means our HDMI TX timing data as below can drive HDMI 1440x2560 portrait mode:    

Color Format: RGB
Color Depth: 8
Pixels Per Clock: 2
Mode: Progressive
Frame Rate: 50Hz
Resolution: 1440x2560 [Custom Mode]
Pixel Clock: 204792000

HSYNC Timing: hav=1440, hfp=70, hsw=35(hsp=0), hbp=045, htot=1590
VSYNC Timing: vav=2560, vfp=12, vsw=02(vsp=0), vbp=002, vtot=2576

 

3. The reference design we running currently can drive normal landscape HDMI panel like 2160p, 1080p, no any problem, so hardware part should be OK. AXI4 streaming data is from Mixer which is different against HDMI TXSS example design which is from TPG, but I don't think problem is at there.

I am really interseted why same HDMI TX parameter can pass example design but not on ZCU104 design.  Of course one is standalone driver, another is linux driver, however for HDMI TX and VTC parts, it is similar. If problem is not on HDMI part, is it still drm_edid issue or other edid parsing issue?

 

Best Regards,

Peter 

 

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Xilinx Employee
Xilinx Employee
220 Views
Registered: ‎08-02-2007

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

@peterjuteoa 

can you read EDID info from your HDMI sink, and see if it supports this resolution?

Please also provide the dmesg log.

Also please provides the wikipage link of the revision design your are using, I will try to do some test at my end.

 

Scholar watari
Scholar
212 Views
Registered: ‎06-16-2013

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

Hi @peterjuteoa 

 

I just ask you "do you want to output 1440x2560 resolution as portrait ?"

 

If no, in other word, you want to output 2560x1440 (horizontal=2560, vertical=1440), you need to modify your code.

 

If yes, I sugeest you to calculate video timing by VESA CVT or refering CEA video timing (keep pixel clock).

 

Best regards,

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Observer peterjuteoa
Observer
183 Views
Registered: ‎04-02-2019

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

Original design source are here:

https://github.com/Xilinx/reVISION-Getting-Started-Guide/blob/master/Docs/design-file-hierarchy.md

https://www.xilinx.com/member/forms/download/design-license-xef.html?filename=zcu104-rv-ss-2018-3.zip

We can read EDID info from the HDMI sink when using original file. (modetest -M xlnx) but not all the time.

But the current rev (we changed mixer height from 2160 to 2560, I guess this is where lead to dmesg errors). There are some kernel patches as well.

PFA four files,

1. one dmesg with errors (portrait 1440x2560 panel)

2. one normal dmesg with landscape monitor (3840x2160)

3&4. kernel source changed files

We will look into the height change issue at our end too. But if you can help do simulation there seeing if there is any more Linux driver code need to be match into our intension of increasing mixer height from 2160 to 2560.

Thank you!

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Xilinx Employee
Xilinx Employee
127 Views
Registered: ‎08-02-2007

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

@peterjuteoa 

Sorry for the late response.

- When I compared two dmesg logs, it seems that 1440x2560 is unsupported dimention for Video Mixer.

You should get a list of supported dimention when typing "modetest -M xlnx"

From your previous reply, it seems HDMI tx is configurated properly.

I think the main issue here is to let mixer plane supporting 1440x2560.

 

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Observer peterjuteoa
Observer
104 Views
Registered: ‎04-02-2019

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

@xud 

We had done a few tests here and agree that mixer is the issue as it seems can not support 2560 (max height is 2160).

The actual width and height used by the core is always 3840x2160 regardless the para we put for this core.

Did you know how to configure the mixer plane? 

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Xilinx Employee
Xilinx Employee
24 Views
Registered: ‎08-02-2007

Re: Design 1440x2560 resolution HDMI output on ZCU104 revision platform (2018.3)

@peterjuteoa 

Other than IP GUI settings, can you check following properties in mixer device tree file?

xlnx,layer-height

From the file below, the default height for xv_mix_master is still 2160 :

https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/display/xlnx/xlnx%2Cmixer.txt

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