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Observer yuko.2828
Observer
372 Views
Registered: ‎12-27-2018

Disable MIPI LP mode in CSI RX subsystem

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Hi,

Can we disable LP mode ?

PG232 does not have any explanation on it.

 

Thanks!

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Xilinx Employee
Xilinx Employee
297 Views
Registered: ‎03-30-2016

Re: Disable MIPI LP mode in CSI RX subsystem

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Hello @yuko.2828 

1. If you are using MIPI CSI-2 TX Subsystem IP,
You can set the Clock mode in Core configuration register. (see PG260 chapter 2 for more detailed information)
XF_TX_CLOCK_MODE.png
2. For MIPI CSI-2 RX Subsystem IP.
RX IP can receive both Continuous and Non-continuous clock mode, without any register setting modification required.

3. For reason (2), we do not mention this setting on PG232. (But MIPI D-PHY document (PG202) do mention that we support both Continuous/Non-continuous clock)

Hope this helps

Thanks,
Leo

3 Replies
Xilinx Employee
Xilinx Employee
348 Views
Registered: ‎03-30-2016

Re: Disable MIPI LP mode in CSI RX subsystem

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Hello,
Short answer: You cannot.


MIPI D-PHY specification introduces LP-mode (Low power mode) to suppress the power consumption during the blanking period ( or non-valid video data period ), LP mode is a must as defined in the specification.

Xilinx MIPI D-PHY/CSI-2 do support continuous clock mode (after initialization, clock lane will always toggling at HS mode), but this feature is only for clock-lane. Data lanes will do HS->LP transition after complete sending HS transmission.

 

Thanks & regards
Leo

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Observer yuko.2828
Observer
305 Views
Registered: ‎12-27-2018

Re: Disable MIPI LP mode in CSI RX subsystem

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Hi Leo,

Glad to know that Xilinx MIPI can receive HS input signal continously.

Thanks, I understand your explanation, I know what LP mode is.

But I think PG232 is not clear on it ?!

Xilinx Employee
Xilinx Employee
298 Views
Registered: ‎03-30-2016

Re: Disable MIPI LP mode in CSI RX subsystem

Jump to solution

Hello @yuko.2828 

1. If you are using MIPI CSI-2 TX Subsystem IP,
You can set the Clock mode in Core configuration register. (see PG260 chapter 2 for more detailed information)
XF_TX_CLOCK_MODE.png
2. For MIPI CSI-2 RX Subsystem IP.
RX IP can receive both Continuous and Non-continuous clock mode, without any register setting modification required.

3. For reason (2), we do not mention this setting on PG232. (But MIPI D-PHY document (PG202) do mention that we support both Continuous/Non-continuous clock)

Hope this helps

Thanks,
Leo