11-01-2017 03:32 PM
I am using the DisplayPort IP in an application which is a test environment where we will connect up a DisplayPort TX chip and want to quickly verify that it passes video correctly. The roadblock currently is that the initial synchronization sequence takes on the order of 5-seconds which for us is an eternity. With the path losses, etc being the same between each chip we test is there a way to have the connection assume a set of correction values and go with it?
11-02-2017 03:43 AM
You should be able to skip the EDID read as you know the sink.
Not sure if that answers what you are asking...
11-02-2017 05:24 AM
11-02-2017 07:03 AM
Yes it would be in the DP source.
I don't think you can bypass the training.
11-06-2017 10:28 PM
Please refer the followings. At least, it's important for DisplayPort.
- Must do link training.
- If the design is for Display Port not eDP, I suggest to implement EDID. It may be confuse DP source, if no EDID.
12-04-2017 02:54 AM
If everything is clear for you on this subject, please kindly mark it as solved by marking a response as solution.