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974 Views
Registered: ‎03-03-2017

DisplayPort custom hardware using different MGTREF port

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Hi,

   I am working on a design using custom hardware which has a Kintex-7 325T -1 device on it and I am using Vivado/SDK 2018.1 and a design with a DisplayPort Rx based on the DisplayPort RxTx example design I generated in 2017.4 I believe.

  On this custom hardware I have routed the DP159 recovered clock to GTREF_0 instead of GTREF_1 which is used in the example design.

  On my design I updated the Video Phy block to select GTREF_0 in the IP customization settings (see below image).

dp_0.png

 

   I can't seem to get the design to work and I am thinking there is something that needs to be updated in the SDK application, but I cannot seem to find any code that specifies which GTREF is being used.

   Can somebody please point me to the code that needs to potentially be updated for this?   The code is based on the KC705 DisplayPort example design.

 

Thanks

Tim

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Registered: ‎03-03-2017

Re: DisplayPort custom hardware using different MGTREF port

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@florentw,

   I think I solved it after much effort.

   It appears that in dppt_vid_phy_cfg.h there is a enum for XVphy_User_GT_RefClk_Src  which sets up which REFCLK is connected to DP159 for DpRx and which is connected to the onboard refclk for DpTx (which I am not using in this design).   It appears that reversing their order makes the setup believe the DP159 is on 0 instead of 1.

   Can you confirm that this was the correct place to update the RECLK setup?

 

dp_3.png

 

Thanks.

Tim

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Registered: ‎11-09-2015

Re: DisplayPort custom hardware using different MGTREF port

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Hi @tim_severance,

 

The video phy requires a default value for the ref clock. However this is controlled by SW at the end.

 

It is done in the video phy config table:

DP159.PNG

 

You just need to be aware that when the clocks DP159_FORWARDED_CLK and ONBOARD_RE_CLK are specified for the HW design. So if you made a change in the HW you need to change their value in SW.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎03-03-2017

Re: DisplayPort custom hardware using different MGTREF port

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@florentw,

   I see I can select DP159_FORWARD_CLK and ONBOARD_REF_CLK in that table, but I don't see anywhere that defines which GTREF port the DP159 forwarded clock goes to.   Or does this all come from the hardware design GTREF selection I outlined in my original post?

Thanks.

Tim

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Registered: ‎03-03-2017

Re: DisplayPort custom hardware using different MGTREF port

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@florentw,

   Somewhere there should be code that tells the VPHY which GTREF IBUFDS to use (see schematic shot below of the implemented design DPrx Vphy block).   I see in the BSP/xphy_v1_7/src/xvphy.c there is a function "void XVphy_IBufDsEnable" which sets up the IBUFDS, but I don't seem to find anything in the DPrx example design that calls this function.

dp_1.png

dp_2.png

   Is it possible that the DPrx requires us to use GTREFCLK_1?

 

Thanks.

Tim

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Registered: ‎03-03-2017

Re: DisplayPort custom hardware using different MGTREF port

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@florentw,

   I think I solved it after much effort.

   It appears that in dppt_vid_phy_cfg.h there is a enum for XVphy_User_GT_RefClk_Src  which sets up which REFCLK is connected to DP159 for DpRx and which is connected to the onboard refclk for DpTx (which I am not using in this design).   It appears that reversing their order makes the setup believe the DP159 is on 0 instead of 1.

   Can you confirm that this was the correct place to update the RECLK setup?

 

dp_3.png

 

Thanks.

Tim

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Registered: ‎11-09-2015

Re: DisplayPort custom hardware using different MGTREF port

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HI @tim_severance,

 

Yes I confirm this is the correct place to change. Sorry I should have give you more details.

 

Just in case you need detail about the value, you can refer to the GT user guide:

GTref.PNG

 

The value 1 is for GTREFCLK0 and 2 for GTREFCLK1. You can also use the value 3->6 if you are using the clock from an adjacent quad (using advance clocking mode in the video PHY).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**