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Observer parithyila
Observer
1,141 Views
Registered: ‎04-09-2019

Displayport TX Subsystem - Native Video Interface

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Hi , I am going to work with Native Video Interface , I am not having the AXI stream interface , if i have a short look in figure 1-1 AXI4-Stream to Video Out Core with the Video Timing Controller from the document AXI4-Stream to Video Out v4.0, i can see the final output as (data, hsync, vsync, active_video, hblank, vblank, field Id) i have attached the reference document for your reference .So my doubt is if i generate (data, hsync, vsync, active_video, hblank, vblank, field Id) internally using our RTL . Can i interface directly with Native Video Interface with MST, will it will work ?.

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Moderator
Moderator
1,074 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

I assume you are talking about the Displayport (I have modified the title of your topic accordingly).

Yes you should be able to generate the timing signals in the RTL directly with the VTC + AXI4-Stream to video out.

In fact, if you look inside the DP core when configured with AXI4-Stream interface, this is what the IP is using under the hood

DP.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
1,075 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

I assume you are talking about the Displayport (I have modified the title of your topic accordingly).

Yes you should be able to generate the timing signals in the RTL directly with the VTC + AXI4-Stream to video out.

In fact, if you look inside the DP core when configured with AXI4-Stream interface, this is what the IP is using under the hood

DP.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer parithyila
Observer
1,044 Views
Registered: ‎04-09-2019

Re: Displayport TX Subsystem - Native Video Interface

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Hi, Thanks for changing the subject, yes I am talking about display port . I am having some Question regarding. 1. There are two mode of interface to the display port a. VTC + AXI4-Stream to video out . b.Native Video Interface . As we see in the data sheet(I have attached the reference doc) the final output of VTC + AXI4-Stream to video out is video interface(data,hsync,vsync,active_video,hblank,v,blank,field_Id). In our design we are having a internal timing generator which will generate the same signal which I said above.my question is can we go with Native Video Interface mode by interfacing our own timing generated signal to interface with the display port. Instead for generating the same signal using VTC + AXI4-Stream to video out? 2.will Native Video Interface Supports multi-stream transport. pls confim this topic asap .
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Moderator
Moderator
1,036 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

Yes you can use your own timing generator. But you have to be aware that if you are using multiple lanes, then you need to "divide" the timing between each lanes.

The easiet remains the use of the AXi4-Stream interface


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Newbie ilam
Newbie
1,024 Views
Registered: ‎04-15-2019

Re: Displayport TX Subsystem - Native Video Interface

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Hi, Thanks for your reply, Will Native Video Interface Supports multi-stream transport.
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Moderator
Moderator
1,014 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @ilam 

Yes, you can use the native interface with MST. As long as the IP GUI allow you a configuration, then it should be supported.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

Do you have any update on this topic? Is everything clear for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer parithyila
Observer
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Registered: ‎04-09-2019

Re: Displayport TX Subsystem - Native Video Interface

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Hi ,

can you clear me what is the difference between pg299 (DisplayPort 1.4 TX Subsystem v2.0) and pg199 ( DisplayPort TX Subsystem v2.1) is it a document version update.which one i need to follow.

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Moderator
Moderator
597 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

There are 2 different IPs:

The Displayport TX Subsystem is the legacy IP which supports DP1.2 specification. Its PG is PG199

The Displayport 1.4 TX subsystem supports the DP1.4 spec and is documented in PG299.

So you need to follow the one corresponding to the IP you are using.

If you are on 7-series devices, only the Displayport TX Subsystem (DP1.2) is available.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer parithyila
Observer
557 Views
Registered: ‎04-09-2019

Re: Displayport TX Subsystem - Native Video Interface

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Hi,

I have refered Native Video Interface page no 13 in the   PG199 document , if i see the blok diagram of Native Video Interface it says that  AXI Interconnect, HDCP controller and AXI Timer will be present only when HDCP is enabled, in my design i am not going to use HDPC. so AXI interconnect will be disabled, if it is disabled than how can i configure the displayport transmitter.

Is it necessary to configure the displayport transmitter ? or it will configured while generating the ip

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Moderator
Moderator
542 Views
Registered: ‎11-09-2015

Re: Displayport TX Subsystem - Native Video Interface

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Hi @parithyila ,

This is a different question. Could you kindly create a new topic for this?

With one topic/question it would be easier for other members to find answers if they have the same question.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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