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Contributor
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Registered: ‎10-04-2018

Enabling PL-DDR

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Hello,

I am using ZCU104 board and working on a project about VCU IP with ZCU104 BSP. I want to enable the PL-DDR; in PG252 page 113 there is a section about it. But I dont think it is well described. I think I need to add some new IPs but I dont know which ones to add. I also dont know how to connect them.

Does anybody have an idea and help me about it, please?

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Moderator
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Registered: ‎11-09-2015

Re: Enabling PL-DDR

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Hi @yildizbilgin 

Yes PG252 page 113, is what you need


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-09-2015

Re: Enabling PL-DDR

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Hi @yildizbilgin 

You need to add the Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP as described in pg252 chapter 6 ...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎10-04-2018

Re: Enabling PL-DDR

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Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP is already in the project. Chapter 6 doesnt explain the PL-DDR, it explain PS-DDR which is already in the project and already connected.
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Registered: ‎11-09-2015

Re: Enabling PL-DDR

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Hi @yildizbilgin

The Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP is to connect the PL DDR. This is explained in the PG., please read it carefully

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎10-04-2018

Re: Enabling PL-DDR

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Hi @florentw ,

 

But The Zynq UltraScale+ EV Architecture Video Codec Unit DDR4 LogiCORE IP is already in the BSP project, what things should i change I still dont know. 

In PG252 page 113, i followed the steps. Is it enough?

 

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Moderator
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Registered: ‎11-09-2015

Re: Enabling PL-DDR

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Hi @yildizbilgin 

Yes PG252 page 113, is what you need


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

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