UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor willenlao
Visitor
1,575 Views
Registered: ‎10-26-2017

HDMI 2.0 VIDEO PHY Controller

We are using the video phy controller in conjunction with the HDMI TX and RX IPs targetting an ultrascale device.

 

I had a few questions about the video phy controller.

 

1.  In our system the master clock source for the HDMI TX (from which the other clocks are derived) is an internally generated pixel clock.  We only need to support 8-bit color depths.  Given this, how would I generate the tx reference clock input from this clock into the video phy?

 

2.  When I enable Advanced Clocking for the video phy, I get refclk_in and refclk_odiv2_in inputs into the video phy controller module.  How do I feed a single ended clock into each of these inputs?  I'm not sure what is expected of refclk_odiv2_in.  

 

3.  When I disable Advanced Clocking for the video phy, I get refclk_in_p and refclk_in_n differential inputs into the module.  How do a feed a single ended clock that is NOT external to the fpga into these inputs?  

 

4.  The video phy controller wizard has an option for number of pixels per clock.  If I configure this to be "1", does that mean the video_clk output generated will have its frequency = pixel clock frequency?  If the answer is "yes", can I divide this video_clk output by 2 and feed the divided down clock into the HDMI TX and RX blocks, since these blocks can only support video clock = 1/2 or 1/4 pixel clock frequency?  

 

5.  The video phy controller user guide says that for GTHE3 transceiver the NI-DRU clock needs to be 156.25 MHz.  However, the video controller wizard has an option for NI-DRU frequency that is defaulted to 100 MHz and that option cannot be changed.  So which is it?  156.25 or 100, or both frequencies are acceptable?  

0 Kudos
4 Replies
Xilinx Employee
Xilinx Employee
1,531 Views
Registered: ‎08-02-2007

Re: HDMI 2.0 VIDEO PHY Controller

Firstly, you can use HDMI example design as reference. The detailed steps on generating HDMI example design can be found in chapter 5 of PG236/PG235

 

1. Please take a look at HDMI Clocking Section(page 46) of PG230

"Connect the external clock generator output clock to the TX reference clock input that was selected in the VPHY GUI. The TX reference clock lock indicator should be connected to the tx_refclk_rdy port."

TX Reference clock can be generated by configurable clock generator. In our example design, we use on-chip Silab clock generator to generate TX reference clock.

 

2. Again you can refer to HDMI example design. If you select Advance clock option, you need to instantiate IBUFDS_GTE manually. If you don't select this option, you can connect reference clock to the clock input pad directly

 

3. As I mentioned in bullet point 2, when you disable Advance clock option, the refclk_in_p and refclk_in_n are expecting the input clock pad. You shouldn't connect internal clock to it.

 

4. You are correct. In the latest version HDMI IP only supports 2ppc and 4ppc, Video PHY ppc setting has to match with HDMI IP

 

If you use different pixels per clock value between Video PHY and HDMI Subsystem, the design will be stuck with following warnings :

---------------------------------

TX cable is connected

Starting colorbar

Warning: HDMI TX SS PPC = 2, doesn't match with VPhy PPC = 4

Unable to set requested TX video resolution.

 

Returning to previously TX video resolution.

 

5.156.25 MHz is correct one, which is the readily available MGTREFCLK on Xilinx dev boards and what the HDMI XAPPs have been validated with. A different clock frequency isn't guaranteed to be working.

 

0 Kudos
Visitor willenlao
Visitor
1,479 Views
Registered: ‎10-26-2017

Re: HDMI 2.0 VIDEO PHY Controller

Thanks for your answers.  I have a few followup questions.  

 

1.  We need to generate a pixel clock for our design.  That is why I suggested having the video phy video_clk output configured for 1 pixel per clock.  To match the HDMI IP video clock (which is 2 pixels per clock), I plan to divide the video phy video_clk output by 2 before feeding this into the HDMI modules.  Are you saying this won't work?  Note that I am NOT trying to re-create the reference design.  I am trying to use the HDMI/Video PHY blocks for our own application.  

 

 

0 Kudos
Xilinx Employee
Xilinx Employee
1,386 Views
Registered: ‎08-02-2007

Re: HDMI 2.0 VIDEO PHY Controller

If you are using your own application, it's possible to make it work. If I remember correctly, the version earlier than Vivado 2017.1 does support 1ppc.

 

As TX driver checks difference between Video PHY and HDMI TX settings, probably you need to do necessary modification. HDMI RX driver won't check it.

0 Kudos
Moderator
Moderator
1,313 Views
Registered: ‎11-09-2015

Re: HDMI 2.0 VIDEO PHY Controller

Hi @willenlao,

 

If everything is clear for you on this subject, please kindly mark it as solved by marking a response as solution.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos